W83627EG Nuvoton Technology Corporation of America, W83627EG Datasheet - Page 149

• Manufacturer Part Number: W83627EG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627EG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The Data Rate Register is used to set the transfer rate and write precompensation. However, in PC-AT
and PS/2 Model 30 and PS/2 modes, the data rate is controlled by the CC register, not by the DR
register. As a result, the real data rate is determined by the most recent write to either the DR or CC
register. The bit definitions for this register are as follows:
S/W RESET (Bit 7):
This bit is the software reset bit.
POWER-DOWN (Bit 6):
0
1
PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2):
These three bits select the value of write precompensation. The following tables show the
precompensation values for every combination of these bits.
2
0
0
0
0
1
1
FDC in normal mode
FDC in power-down mode
PRECOMP
1
0
0
1
1
0
0
0
0
1
0
1
0
1
7
6
5
0
250K - 1 Mbps
Default Delays
4
125.00 ns
166.67 ns
208.33 ns
41.67 ns
83.34 ns
3
W83627EHF/EF, W83627EHG/EG
- 138 -
2
PRECOMPENSATION DELAY
1
0
DRATE0
DRATE1
PRECOMP0
PRECOMP1
PRECOMP2
POWER DOWN
S/W RESET
2 Mbps Tape drive
Default Delays
41.17 ns
104.2 ns
20.8 ns
83.3 ns
62.5ns