PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 93

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
14.1.42
PORT OPTION REGISTER – OFFSET 74h
Bit
19
20
21
22
23
Bit
0
1
2
3
Function
Target Abort
during Posted
Write
Master Abort
during Posted
Write
Delayed Write
Non-delivery
Delayed Read –
No Data from
Target
Delayed
Transaction
Master Timeout
Function
Reserved
Primary MEMR
Command Alias
Enable
Primary MEMW
Command Alias
Enable
Secondary
MEMR
Command Alias
Enable
Type
R/WC
R/WC
R/WC
R/WC
R/WC
Type
R/O
R/W
R/W
R/W
Page 93 of 111
Description
1: Signal P_SERR_L was asserted because the bridge received a
target abort when delivering post memory write data.
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge received a
master abort when attempting to deliver post memory write data
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver delayed write data after 2
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
read any data from the target after 2
Reset to 0.
1: Signal P_SERR_L was asserted because a master did not repeat a
read or write transaction before master timeout.
Reset to 0.
Description
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C8150A’s detection mechanism for matching memory
read retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from the initiator on the primary interface
Reset to 0
Controls PI7C8150A’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the primary interface
Reset to 0
Controls PI7C8150A’s detection mechanism for matching memory
read retry cycles from the initiator on the secondary
0: exact matching for memory read retry cycles from initiator on the
secondary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from initiator on the secondary interface
Reset to 0
2-PORT PCI-TO-PCI BRIDGE
24
APRIL 2006 – Revision 1.1
attempts.
24
attempts.
PI7C8150A