PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 22

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
3.1
3.2
Table 3-1. PCI Transactions
Types of Transactions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C8150A.
Table 3-1 lists the command code and name of each PCI transaction. The Master and
Target columns indicate support for each transaction when PI7C8150A initiates
transactions as a master, on the primary (P) and secondary (S) buses, and when PI7C8150A
responds to transactions as a target, on the primary (P) and secondary (S) buses.
SINGLE ADDRESS PHASE
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and
the bus command is driven on P_CBE[3:0]. PI7C8150A supports the linear increment
address mode only, which is indicated when the lowest two address bits are equal to zero.
As indicated in Table 3-1, the following PCI commands are not supported by
PI7C8150A:
PI7C8150A never initiates a PCI transaction with a reserved command code and, as
a target, PI7C8150A ignores reserved command codes.
PI7C8150A does not generate interrupt acknowledge transactions. PI7C8150A
ignores interrupt acknowledge transactions as a target.
PI7C8150A does not respond to special cycle transactions. PI7C8150A cannot
guarantee delivery of a special cycle transaction to downstream buses because of the
broadcast nature of the special cycle command and the inability to control the
transaction as a target. To generate special cycle transactions on other PCI buses,
either upstream or downstream, Type 1 configuration write must be used.
PI7C8150A neither generates Type 0 configuration transactions on the primary PCI
bus nor responds to Type 0 configuration transactions on the secondary PCI buses.
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
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Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Secondary
N
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
Responds as Target
Primary
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
PI7C8150A
N
N
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Secondary
Y