PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 73

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
12
12.1
Table 11-1. Power Management Transitions
Table 11-1 shows the states and related actions that PI7C8150A performs during power
management transitions. (No other transactions are permitted.)
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME#
signals do not pass through PCI-to-PCI bridges.
RESET
This chapter describes the primary interface, secondary interface, and chip reset
mechanisms.
PRIMARY INTERFACE RESET
PI7C8150A has a reset input, P_RESET_L. When P_RESET_L is asserted, the following
events occur:
P_RESET_L asserting and de-asserting edges can be asynchronous to P_CLK and
S_CLKOUT. PI7C8150A is not accessible during P_RESET_L. After P_RESET_L is de-
asserted, PI7C8150A remains inaccessible for 16 PCI clocks before the first configuration
transaction can be accepted.
D0
D0
D0
D0
D3hot
D3hot
D3cold
Current Status
Support of the B2 secondary bus power state when in the D3
state
PI7C8150A immediately tri-states all primary and secondary PCI interface signals.
PI7C8150A performs a chip reset.
Registers that have default values are reset.
D3cold
D3hot
D2
D1
D0
D3cold
D0
Next State
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Power has been removed from PI7C8150A. A power-up reset must
be performed to bring PI7C8150A to D0.
If enabled to do so by the BPCCE pin, PI7C8150A will disable the
secondary clocks and drive them LOW.
Unimplemented power state. PI7C8150A will ignore the write to the
power state bits (power state remains at D0).
Unimplemented power state. PI7C8150A will ignore the write to the
power state bits (power state remains at D0).
PI7C8150A enables secondary clock outputs and performs an internal
chip reset. Signal S_RST_L will not be asserted. All registers will
be returned to the reset values and buffers will be cleared.
Power has been removed from PI7C8150A. A power-up reset must
be performed to bring PI7C8150A to D0.
Power-up reset. PI7C8150A performs the standard power-up reset
functions as described in Section 12.
2-PORT PCI-TO-PCI BRIDGE
Action
APRIL 2006 – Revision 1.1
hot
power management
PI7C8150A