PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 55

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
When a delayed write transaction is normally queued, the address, command, address
parity, data, byte enable bits, and data parity are all captured and a target retry is returned to
the initiator. When PI7C8150A detects a parity error on the write data for the initial
delayed write request transaction, the following events occur:
Note: If parity checking is turned off and data parity errors have occurred for queued or
subsequent delayed write transactions on the initiator bus, it is possible that the initiator’s
re-attempts of the write transaction may not match the original queued delayed write
information contained in the delayed transaction queue. In this case, a master timeout
condition may occur, possibly resulting in a system error (P_SERR_L assertion).
For downstream transactions, when PI7C8150A is delivering data to the target on the
secondary bus and S_PERR_L is asserted by the target, the following events occur:
Similarly, for upstream transactions, when PI7C8150A is delivering data to the target on
the primary bus and P_PERR_L is asserted by the target, the following events occur:
A delayed write transaction is completed on the initiator bus when the initiator repeats the
write transaction with the same address, command, data, and byte enable bits as the
delayed write command that is at the head of the posted data queue. Note that the parity bit
is not compared when determining whether the transaction matches those in the delayed
transaction queues.
Two cases must be considered:
If the parity-error-response bit corresponding to the initiator bus is set, PI7C8150A
asserts TRDY_L to the initiator and the transaction is not queued. If multiple data
phases are requested, STOP_L is also asserted to cause a target disconnect. Two cycles
after the data transfer, PI7C8150A also asserts PERR_L.
If the parity-error-response bit is not set, PI7C8150A returns a target retry. It queues
the transaction as usual. PI7C8150A does not assert PERR_L. In this case, the
initiator repeats the transaction.
PI7C8150A sets the detected-parity-error bit in the status register corresponding to the
initiator bus, regardless of the state of the parity-error-response bit.
PI7C8150A sets the secondary interface data parity detected bit in the secondary status
register, if the secondary parity error response bit is set in the bridge control register.
PI7C8150A captures the parity error condition to forward it back to the initiator on the
primary bus.
PI7C8150A sets the primary interface data-parity-detected bit in the status register, if
the primary parity-error-response bit is set in the command register.
PI7C8150A captures the parity error condition to forward it back to the initiator on the
secondary bus.
When parity error is detected on the initiator bus on a subsequent re-attempt of the
transaction and was not detected on the target bus
When parity error is forwarded back from the target bus
Page 55 of 111
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A