LM93CIMT/NOPB National Semiconductor, LM93CIMT/NOPB Datasheet - Page 55

• Manufacturer Part Number: LM93CIMT/NOPB
• Description: IC HARDWARE MONITOR 56-TSSOP
• Manufacturer: National Semiconductor

Specifications of LM93CIMT/NOPB

• Applications: Monitors
• Interface: 2-Wire SMBus
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 56-TSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM93CIMT; *LM93CIMT/NOPB; LM93CIMT

Register
Address
Register
Address
Register
Address
16.0 Registers
16.6.8 Register 6Bh GPI State
16.6.9 Register 6Ch P1_VID
16.6.10 Register 6Dh P2_VID
6Bh
6Ch
6Dh
Read/
Write
Read/
Read/
Write
Write
R
R
R
GPI State
5:0
7:6
5:0
7:6
Register
Bit
Register
Bit
Register
Bit
P1_VID
P2_VID
0
1
2
3
4
5
6
7
Name
Name
Name
(Continued)
P1_VID
P2_VID
Name
Name
Name
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
GPI7
RES
RES
Bit 7
Bit 7
Bit 7
GPI7
Read/Write
Read/Write
Read/Write
RES
RES
R
R
R
R
R
R
R
R
R
R
R
R
GPI6
Bit 6
Bit 6
Bit 6
1 if GPIO_0 input is LOW
1 if GPIO_1 input is LOW
1 if GPIO_2 input is LOW
1 if GPIO_3 input is LOW
1 if GPIO_4 input is LOW
1 if GPIO_5 input is LOW
1 if GPIO_6 input is LOW
1 if GPIO_7 input is LOW
Processor 1 VID status.
Reports the current value of the P1_VID5
through P1_VID0 pins. This register should
only be updated if P1_VID5 through P1_VID0
remain stable for at least 600 ns.
Reserved
Processor 2VID status.
Reports the current value of the P2_VID5
through P2_VID0 pins. This register should
only be updated if P2_VID5 through P2_VID0
remain stable for at least 600 ns.
Reserved
GP15
Bit 5
Bit 5
Bit 5
55
Bit 4
Bit 4
Bit 4
GPI4
Description
Description
Description
Bit 3
Bit 3
GPI3
Bit 3
P1_VID
P2_VID
Bit 2
Bit 2
Bit 2
GPI2
Bit 1
Bit 1
GPI1
Bit 1
Bit 0
Bit 0
Bit 0
GPI0
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Default
Default
Default
Value
Value
Value
N/D
N/D
N/D