LM93CIMT/NOPB National Semiconductor, LM93CIMT/NOPB Datasheet - Page 45

• Manufacturer Part Number: LM93CIMT/NOPB
• Description: IC HARDWARE MONITOR 56-TSSOP
• Manufacturer: National Semiconductor

Specifications of LM93CIMT/NOPB

• Applications: Monitors
• Interface: 2-Wire SMBus
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 56-TSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM93CIMT; *LM93CIMT/NOPB; LM93CIMT

Register
Address
Bit
7:4
Register
Address
Bit
7:6
16.0 Registers
16.4.8 Register 47h B_Fan Error Status
16.5 HOST ERROR STATUS REGISTERS
The Host Error Status Registers contain several bits that each represent a particular error event that the LM93 can monitor. The
LM93 sets a given bit whenever the corresponding error event occurs. The HOST_ERR bit in the LM93 Status/Control register
also sets if any bit in the Host Error Status registers is set. The exception to this is the fixed threshold error status bits in the
PROCHOT Error Status registers. They have no influence on HOST_ERR.
Once a bit is set in the Host Error Status registers, it is not automatically cleared by the LM93 if the error event goes away. Each
bit must be cleared by software. If software attempts to clear a bit while the error condition still exists, the bit does not clear.
Software must specifically write a 1 to any bits it wishes to clear in the Host Error Status registers (write-one-to-clear).
Each register described in this section has a column labeled Sleep Masking. This column describes which error events are
masked in various sleep states. The sleep state of the system is communicated to the LM93 by writing to the Sleep State Control
register. If a sleep state in this column has a ‘*’ next to it, it denotes that the error event is optionally masked in that sleep mode,
depending on the Sleep State Mask registers.
16.5.1 Register 48h H_Error Status 1
0
1
2
3
0
1
2
3
4
5
47h
48h
FAN1_ERR
FAN2_ERR
FAN3_ERR
FAN4_ERR
RES
ZN1_ERR
ZN2_ERR
ZN3_ERR
ZN4_ERR
VRD1_ERR
VRD2_ERR
RES
Name
Name
Read/
Read/
Write
RWC
Write
RWC
Error Status
Register
Status 1
H_Error
Register
Name
RWC This bit is set when the Fan Tach 1 value register is above the value set in
RWC This bit is set when the Fan Tach 2 value register is above the value set in
RWC This bit is set when the Fan Tach 3 value register is above the value set in
RWC This bit is set when the Fan Tach 4 value register is above the value set in
RWC This bit is set when the zone 1 temperature has fallen outside the zone 1
RWC This bit is set when the zone 2 temperature has fallen outside the zone 2
RWC This bit is set when the zone 3 temperature has fallen outside the zone 3
RWC This bit is set when the zone 4 temperature has fallen outside the zone 4
RWC This bit is set when the VRD1_HOT input has been asserted.
RWC This bit is set when the VRD2_HOT input has been asserted.
R/W
R/W
B_Fan
(Continued)
Name
R
R
the Fan Tach 1 Limit register.
the Fan Tach 2 Limit register.
the Fan Tach 3 Limit register.
the Fan Tach 4 Limit register.
Reserved
temperature limits.
temperature limits.
temperature limits.
temperature limits.
Reserved
Bit 7
Bit 7
RES
Bit 6
Bit 6
RES
VRD2
_ERR
Bit 5
Bit 5
45
Description
Description
VRD1
_ERR
Bit 4
Bit 4
_ERR
_ERR
FAN4
Bit 3
Bit 3
ZN4
_ERR
_ERR
FAN3
Bit 2
Bit 2
ZN3
_ERR
_ERR
FAN2
Bit 1
Bit 1
ZN2
_ERR
_ERR
FAN1
Bit 0
Bit 0
ZN1
S1*, S3*, S4/5
S1*, S3*, S4/5
S1*, S3*, S4/5
S1*, S3*, S4/5
S3*, S4/5*
S3*, S4/5*
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Masking
Masking
S3, S4/5
S3, S4/5
Sleep
Sleep
none
none
N/A
N/A
Default
Default
Value
Value
00h
00h