LM93CIMT/NOPB National Semiconductor, LM93CIMT/NOPB Datasheet - Page 52

• Manufacturer Part Number: LM93CIMT/NOPB
• Description: IC HARDWARE MONITOR 56-TSSOP
• Manufacturer: National Semiconductor

Specifications of LM93CIMT/NOPB

• Applications: Monitors
• Interface: 2-Wire SMBus
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 56-TSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM93CIMT; *LM93CIMT/NOPB; LM93CIMT

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Register
Address
Register
Address
Bit
7:4
Register
Address
16.0 Registers
16.5.8 Register 4Fh H_Fan Error Status
16.6 VALUE REGISTERS
16.6.1 Registers 50–53h Unfiltered Temperature Value Registers
Zones 1, 2 and 3 are all automatically updated by the LM93. The Zone 4 (External Digital) Temp register must be written by an
external SMBus device.
The temperature registers for zones 1 and 2 must return a value of 80h if the remote diode pins are not implemented by the board
designer or are not functioning properly.
16.6.2 Registers 54–55h Filtered Temperature Value Registers
These registers reflect the temperature of zones 1 and 2 after the spike smoothing filter has been applied.
The characteristics of the filtering can be adjusted by using the Zones 1/2 Spike Smoothing Control register.
0
1
2
3
50h
51h
52h
53h
4Fh
54h
55h
FAN1_ERR
FAN2_ERR
FAN3_ERR
FAN4_ERR
RES
Name
Read/
Write
Read/
R/W
Read/
Write
RWC
Write
R
R
R
R
R
Zone 3 (Internal) Temp
(External Digital) Temp
Zone 1 (CPU1) Temp
Zone 2 (CPU1) Temp
Error Status
Zone 1 (CPU1)
Zone 2 (CPU1)
Filtered Temp
Filtered Temp
Register
RWC This bit is set when the Fan Tach 1 value register is above the value set in
RWC This bit is set when the Fan Tach 2 value register is above the value set in
RWC This bit is set when the Fan Tach 3 value register is above the value set in
R/W
H_Fan
(Continued)
Name
Register
R
R
Name
Register
Zone 4
Name
the Fan Tach 1 Limit register.
the Fan Tach 2 Limit register.
the Fan Tach 3 Limit register.
This bit is set when the Fan Tach 4 value register is above the value set in
the Fan Tach 4 Limit register.
Reserved
Bit 7
Bit 7
7
7
Bit 7
Bit 6
7
7
7
7
Bit 6
RES
6
6
Bit 6
Bit 5
6
6
6
6
52
Bit 5
5
5
Description
Bit 5
Bit 4
5
5
5
5
Bit 4
4
4
Bit 4
4
4
4
4
_ERR
FAN4
Bit 3
Bit 3
3
3
Bit 3
3
3
3
3
_ERR
FAN3
Bit 2
Bit 2
2
2
Bit 2
2
2
2
2
_ERR
FAN2
Bit 1
Bit 1
Bit 1
1
1
1
1
1
1
_ERR
FAN1
Bit 0
Bit 0
Bit 0
0
0
0
0
0
0
S1*, S3*, S4/5
S1*, S3*, S4/5
S1*, S3*, S4/5
S1*, S3*, S4/5
Masking
Sleep
N/A
Default
Default
Default
Value
Value
Value
00h
00h
00h
N/D
N/D
N/D
N/D