ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 4

• Manufacturer Part Number: ST92F120V1Q7
• Description: Microcontrollers (MCU) Flash 128K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST92F120V1Q7

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 16 Channel
• Lead Free Status / Rohs Status: No

ST92F120 - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92F120 microcontroller is developed and
manufactured by STMicroelectronics using a pro-
prietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register pro-
gramming model for ultra-fast context switching
and real-time event response. The intelligent on-
chip peripherals offload the ST9 core from I/O and
data management processing tasks allowing criti-
cal application tasks to get the maximum use of
core resources. The new-generation ST9 MCU
devices now also support low power consumption
and low voltage operation for power-efficient and
low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File, the Inter-
rupt and DMA controller, and the Memory Man-
agement Unit. The MMU allows a single linear ad-
dress space of up to 4 Mbytes.
Four independent buses are controlled by the
Core: a 16-bit memory bus, an 8-bit register data
bus, an 8-bit register address bus and a 6-bit inter-
rupt/DMA bus which connects the interrupt and
DMA controllers in the on-chip peripherals with the
core.
This multiple bus architecture makes the ST9 fam-
ily devices highly efficient for accessing on and off-
chip memory and fast exchange of data with the
on-chip peripherals.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
The powerful I/O capabilities demanded by micro-
controller
ST92F120 with 77 I/O lines dedicated to digital In-
put/Output. These lines are grouped into up to ten
8-bit I/O Ports and can be configured on a bit basis
under software control to provide timing, status
signals, an address/data bus for interfacing to the
external memory, timer inputs and outputs, analog
inputs, external interrupts and serial or parallel I/O.
Two memory spaces are available to support this
wide range of configurations: a combined Pro-
gram/Data Memory Space and the internal Regis-
4/324
9
applications
are
fulfilled
by
the
ter File, which includes the control and status reg-
isters of the on-chip peripherals.
1.1.2 External Memory Interface
100-pin devices have a 16-bit external address
bus allowing them to address up to 64K bytes of
external memory.
1.1.3 Flash and E3PROM Memories
In the ST92F120, the embedded Flash memory
cell is used to implement emulated EEPROM ca-
pability for applications that require regular up-
dates of single-byte parameters.
1.1.4 On-chip Peripherals
Two 16-bit MultiFunction Timers, each with an 8
bit Prescaler and 12 operating modes allow simple
use for complex waveform generation and meas-
urement, PWM functions and many other system
timing functions by the usage of the two associat-
ed DMA channels for each timer.
Two Extended Function Timers provide further
timing and signal generation capabilities.
A Standard Timer can be used to generate a sta-
ble time base independent from the PLL.
An I
support.
The SPI is a synchronous serial interface for Mas-
ter and Slave device communication. It supports
single master and multimaster systems.
A J1850 Byte Level Protocol Decoder is available
(on some devices only) for communicating with a
J1850 network.
In addition, there is an 16 channel Analog to Digital
Converters with integral sample and hold, fast
conversion time and 8-bit resolution.
Completing the device are two or one full duplex
Serial Communications Interfaces with an integral
generator, asynchronous and synchronous capa-
bility (fully programmable format) and associated
address/wake-up option, plus two DMA channels.
Finally, a programmable PLL Clock Generator al-
lows the usage of standard 3 to 5 MHz crystals to
obtain a large range of internal frequencies up to
24MHz. Low power Run (SLOW), Wait For Inter-
rupt, low power Wait For Interrupt, STOP and
HALT modes are also available.
2
C interface provides fast I
2
C and Access Bus