ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 156

Microcontrollers (MCU) Flash 128K SPI/I2C

ST92F120V1Q7

Manufacturer Part Number
ST92F120V1Q7
Description
Microcontrollers (MCU) Flash 128K SPI/I2C
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST92F120V1Q7

Data Bus Width
8 bit, 16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
77
Number Of Timers
5
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
PQFP-100
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 16 Channel
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST92F120V1Q7
Manufacturer:
ST
Quantity:
6 765
Part Number:
ST92F120V1Q7
Manufacturer:
ST
0
Part Number:
ST92F120V1Q7
Manufacturer:
ST
Quantity:
20 000
Part Number:
ST92F120V1Q7C
Manufacturer:
ST
0
Part Number:
ST92F120V1Q7C
Manufacturer:
ST
Quantity:
20 000
Part Number:
ST92F120V1Q7D/TR
Manufacturer:
ST
0
Part Number:
ST92F120V1Q7DTR
Manufacturer:
MAXIM
Quantity:
2 854
MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER (Cont’d)
The configuration of each input is programmed in
the Input Control Register.
Each of the two output pins can be driven from any
of three possible sources:
– Compare Register 0 logic
– Compare Register 1 logic
– Overflow/Underflow logic
Each of these three sources can cause one of the
following four actions, independently, on each of
the two outputs:
– Nop, Set, Reset, Toggle
In addition, an additional On-Chip Event signal can
be generated by two of the three sources men-
tioned above, i.e. Over/Underflow event and Com-
pare 0 event. This signal can be used internally to
Figure 84. Detailed Block Diagram
156/324
9
synchronise another on-chip peripheral. Five
maskable interrupt sources referring to an End Of
Count condition, 2 input captures and 2 output
compares, can generate 3 different interrupt re-
quests (with hardware fixed priority), pointing to 3
interrupt routine vectors.
Two independent DMA channels are available for
rapid data transfer operations. Each DMA request
(associated with a capture on the REG0R register,
or with a compare on the CMP0R register) has pri-
ority over an interrupt request generated by the
same source.
A SWAP mode is also available to allow high
speed continuous transfers (see Interrupt and
DMA chapter).

Related parts for ST92F120V1Q7