ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 70
ST92F120V1Q7
Manufacturer Part Number
ST92F120V1Q7
Description
Microcontrollers (MCU) Flash 128K SPI/I2C
Manufacturer
STMicroelectronics
Datasheet
1.ST92F120V9Q7.pdf
(325 pages)
Specifications of ST92F120V1Q7
Data Bus Width
8 bit, 16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
77
Number Of Timers
5
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
PQFP-100
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 16 Channel
Lead Free Status / Rohs Status
No
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ST92F120 - INTERRUPTS
ARBITRATION MODES (Cont’d)
re-enabled, they will be acknowledged regardless
of the interrupt service routine’s priority. This may
cause undesirable interrupt response sequences.
Examples
In the following two examples, three interrupt re-
quests with different priority levels (2, 3 & 4) occur
simultaneously during the interrupt 5 service rou-
tine.
Figure 32. Simple Example of a Sequence of Interrupt Requests with:
- Concurrent mode selected and
- IEN unchanged by the interrupt routines
70/324
9
0
1
2
3
4
5
6
7
CPL is set to 7
Priority Level of
Interrupt Request
MAIN
INT 5
ei
CPL = 7
INT 5
INT 2
INT 3
INT 4
CPL = 7
INT 2
CPL = 7
INT 3
CPL = 7
Example 1
In the first example, (simplest case,
ei instruction is not used within the interrupt serv-
ice routines. This means that no new interrupt can
be serviced in the middle of the current one. The
interrupt routines will thus be serviced one after
another, in the order of their priority, until the main
program eventually resumes.
INT 4
CPL = 7
MAIN
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
Figure
32) the
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