ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 50

• Manufacturer Part Number: ST92F120V1Q7
• Description: Microcontrollers (MCU) Flash 128K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST92F120V1Q7

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 16 Channel
• Lead Free Status / Rohs Status: No

ST92F120 - SINGLE VOLTAGE FLASH & EEPROM
3.6 PROTECTION STRATEGY
The protection bits are stored in the last 4 loca-
tions of the TestFlash (from 231FFCh) (see
25).
All the available protections are forced active dur-
ing reset, then in the initialisation phase they are
read from the TestFlash.
The protections are stored in 2 Non Volatile Regis-
ters. Other 2 Non Volatile Registers can be used
as a password to re-enable test modes once they
have been disabled.
The protections can be programmed using the Set
Protection operation (see Control Registers para-
graph), that can be executed from all the internal
or external memories except the Flash or Test-
Flash itself.
The TestFlash area (230000h to 231F7Fh) is al-
ways protected against write access.
Figure 25. Protection Map
3.6.1 Non Volatile Registers
The 4 Non Volatile Registers used to store the pro-
tection bits for the different protection features are
one time programmable by the user, but they are
erasable in Test mode (if not disabled).
Access to these registers is controlled by the pro-
tections related to the TestFlash where they are
mapped. Since the code to program the Protection
Registers cannot be fetched by the Flash or the
TestFlash memories, this means that, once the
APRO or APBR bits in the NVAPR register are
programmed, it is no longer possible to modify any
of the protection bits. For this reason the NV Pass-
word, if needed, must be set with the same Set
Protection operation used to program these bits.
For the same reason it is strongly advised to never
program the WPBR bit in the NVWPR register, as
this will prevent any further write access to the
50/324
9
231FFCh
231FFDh
231FFEh
231FFFh
Protection
NVPWD0
NVWPR
NVPWD1
NVAPR
Figure
TestFlash, and consequently to the Protection
Registers.
NON VOLATILE ACCESS PROTECTION REG-
ISTER (NVAPR)
Address: 231FFCh - Read/Write
Delivery value: 1111 1111 (FFh)
Bit 7 = Reserved.
Bit 6 = APRO: Flash Access Protection.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the Flash
address space (EEPROM excluded), unless the
current instruction is fetched from the TestFlash or
from the Flash itself.
0: Flash protection on
1: Flash protection off
Bit 5 = APBR: TestFlash Access Protection.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the Test-
Flash address space, unless the current instruc-
tion is fetched from the TestFlash itself.
0: TestFlash protection on
1: TestFlash protection off
Bit 4 = APEE: EEPROM Access Protection.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the EEP-
ROM address space, unless the current instruc-
tion is fetched from the TestFlash or from the
Flash, or from the EEPROM itself.
0: EEPROM protection on
1: EEPROM protection off
Bit 3 = APEX: Access Protection from External
Memory.
This bit, if programmed at 0, disables any access
(read/write) to operands mapped inside the ad-
dress space of one of the internal memories (Test-
Flash, Flash, EEPROM, RAM), if the current in-
struction is fetched from an external memory.
7
1
APRO APBR APEE APEX PWT2 PWT1 PWT0
6
5
4
3
2
1
0