DS3154+ Maxim Integrated Products, DS3154+ Datasheet - Page 5

• Manufacturer Part Number: DS3154+
• Description: IC LIU DS3/E3/STS1 QUAD 144CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3154+

• Number Of Drivers/receivers: 4/4
• Protocol: IEEE 1149.1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FEATURES (continued)
Receiver
Transmitter
1. DETAILED DESCRIPTION
The DS3151 (single), DS3152 (dual), DS3153 (triple), and DS3154 (quad) LIUs perform the functions necessary
for interfacing at the physical layer to DS3, E3, or STS-1 lines. Each LIU has independent receive and transmit
paths and a built-in jitter attenuator. The receiver performs clock and data recovery from a B3ZS- or HDB3-coded
alternate mark inversion (AMI) signal and monitors for loss of the incoming signal. The receiver optionally performs
B3ZS/HDB3 decoding and outputs the recovered data in either binary or bipolar format. The transmitter accepts
data in either binary or bipolar format, optionally performs B3ZS/HDB3 encoding, and drives standard pulse-shape
waveforms onto 75Ω coaxial cable. The jitter attenuator can be mapped into the receiver data path, mapped into
the transmitter data path, or be disabled. The DS315x LIUs conform to the telecommunications standards listed in
Table
AGC/equalizer block handles from 0 to 15dB of cable loss
Loss-of-lock (LOL) PLL status indication
Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp
Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ITU G.775)
Optional B3ZS/HDB3 decoder
Line-code violation output pin and counter
Binary or bipolar framer interface
On-board 2
Clock inversion for glueless interfacing
Tri-state clock and data outputs support protection switching applications
Per-channel power-down control
Binary or bipolar framer interface
Gapped clock capable up to 51.84MHz
Wide 50 ±20% transmit clock duty cycle
Clock inversion for glueless interfacing
Optional B3ZS/HDB3 encoder
On-board 2
Complete DS3 AIS generator (ANSI T1.107)
Unframed all-ones generator (E3 AIS)
Line build-out (LBO) control
Tri-state line driver outputs support protection switching applications
Per-channel power-down control
Output driver monitor
1-A.
Figure 1-1
15
15
- 1 and 2
- 1 and 2
shows the external components required for proper operation.
23
23
- 1 PRBS detector
- 1 PRBS generator
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
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