DS3154+ Maxim Integrated Products, DS3154+ Datasheet - Page 15

• Manufacturer Part Number: DS3154+
• Description: IC LIU DS3/E3/STS1 QUAD 144CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3154+

• Number Of Drivers/receivers: 4/4
• Protocol: IEEE 1149.1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5. REGISTER DESCRIPTIONS
When the DS315x is configured in CPU bus mode (HW = 0), the registers shown in
through the CPU bus interface. All registers for the LIU ports are forced to their default values during an internal
power-on reset or when the RST pin is driven low. Setting an LIU’s RST bit high forces all registers for that LIU to
their default values. All register bits marked “—” must be written 0 and ignored when read. The TEST registers
must be left at their reset value of 00h for normal operation.
On the DS3153, only registers for LIUs 1, 2, and 3 are available. Writes into LIU 4 address space are ignored.
Reads from LIU 4 address space return all zeros. On the DS3152, address line A5 is not present, limiting the
address space to the LIU 1 and 2 registers. On the DS3151, address lines A5 and A4 are not present, limiting the
address space to the LIU 1 registers.
Table 5-A. Register Map
Note 1: Underlined bits are read-only; all other bits are read-write.
Note 2: The registers are named REGn, where n = the LIU number (1, 2, 3, or 4).
Note 3: The bit names are the same for each LIU register set.
ADDRESS
08h–0Fh
18h–1Fh
28h–2Fh
38h–3Fh
00h
01h
02h
03h
04h
05h
06h
07h
10h
11h
12h
13h
14h
15h
16h
17h
20h
21h
22h
23h
24h
25h
26h
27h
30h
31h
32h
33h
34h
35h
36h
37h
REGISTER
RCVH1
RCVH2
RCVH3
RCVH4
RCVL1
RCVL2
RCVL3
RCVL4
GCR1
SRIE1
GCR2
SRIE2
GCR3
SRIE3
GCR4
SRIE4
RCR1
TCR2
RCR2
RCR3
RCR4
TCR1
SRL1
TEST
SRL2
TEST
TCR3
SRL3
TEST
TCR4
SRL4
TEST
SR1
SR2
SR3
SR4
RCV[15]
RCV[15]
RCV[15]
RCV[15]
RCV[7]
RCV[7]
RCV[7]
RCV[7]
BIT 7
E3M
E3M
E3M
E3M
ITU
ITU
ITU
ITU
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
RCV[14]
RCV[14]
RCV[14]
RCV[14]
RCV[6]
RCV[6]
RCV[6]
RCV[6]
BIT 6
RBIN
RBIN
RBIN
RBIN
TBIN
TBIN
TBIN
TBIN
STS
STS
STS
STS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RCV[13]
RCV[13]
RCV[13]
RCV[13]
15 of 61
RCV[5]
RCV[5]
RCV[5]
RCV[5]
RCINV
TDMIE
RCINV
TDMIE
RCINV
TDMIE
RCINV
TDMIE
TCINV
TCINV
TCINV
TCINV
TDML
TDML
TDML
TDML
BIT 5
TDM
TDM
TDM
TDM
LLB
LLB
LLB
LLB
LIU 1
LIU 2
LIU 3
LIU 4
—
—
—
—
RCV[12]
RCV[12]
RCV[12]
RCV[12]
PRBSIE
PRBSIE
PRBSIE
PRBSIE
PRBSL
RCV[4]
PRBSL
RCV[4]
PRBSL
RCV[4]
PRBSL
RCV[4]
PRBS
PRBS
PRBS
PRBS
BIT 4
RLB
RJA
RLB
RJA
RLB
RJA
RLB
RJA
TJA
TJA
TJA
TJA
—
—
—
—
RCV[11]
RCV[11]
RCV[11]
RCV[11]
PBERIE
PBERIE
PBERIE
PBERIE
PBERL
PBERL
PBERL
PBERL
RCV[3]
RCV[3]
RCV[3]
RCV[3]
TDSA
TDSA
TDSA
TDSA
BIT 3
RPD
RPD
RPD
RPD
TPD
TPD
TPD
TPD
—
—
—
—
—
—
—
—
RCV[10]
RCV[10]
RCV[10]
RCV[10]
RCV[2]
RCV[2]
RCV[2]
RCV[2]
RCVIE
RCVIE
RCVIE
RCVIE
TDSB
RCVL
TDSB
RCVL
TDSB
RCVL
TDSB
RCVL
BIT 2
RTS
RTS
RTS
RTS
TTS
TTS
TTS
TTS
—
—
—
—
—
—
—
—
Table 5-A
RLOLIE
RLOLIE
RLOLIE
RLOLIE
RCV[1]
RCV[9]
RCV[1]
RCV[9]
RCV[1]
RCV[9]
RCV[1]
RCV[9]
RMON
RLOLL
RMON
RLOLL
RMON
RLOLL
RMON
RLOLL
TLBO
RLOL
TLBO
RLOL
TLBO
RLOL
TLBO
RLOL
BIT 1
—
—
—
—
—
—
—
--
are accessible
RCVUD
RLOSIE
RCVUD
RLOSIE
RCVUD
RLOSIE
RCVUD
RLOSIE
RLOSL
RLOSL
RLOSL
RLOSL
RCV[0]
RCV[8]
RCV[0]
RCV[8]
RCV[0]
RCV[8]
RCV[0]
RCV[8]
RLOS
RLOS
RLOS
RLOS
BIT 0
RST
RST
RST
RST
—
—
—
—
—
—
—
--