NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 9

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

List of Tables
Table 6-1 Devices of I/O Base Address .......................................................................................... 23
Table 6-2 Chip (Global) Control Registers ...................................................................................... 26
Table 7-1 Temperature Data Format .............................................................................................. 34
Table 7-2 SST Command Summary ............................................................................................... 37
Table 7-3 Typical Temperature Values ........................................................................................... 38
Table 7-4 Fan Divisor Definition...................................................................................................... 42
Table 7-5 Divisor, RPM, and Count Relation .................................................................................. 42
TM
Table 7-6 Display Registers – at SMART FAN
I Mode................................................................ 46
TM
Table 7-7 Relative Registers – at Thermal Cruise
Mode............................................................. 47
TM
Table 7-8 Relative Registers – at Speed Cruise
Mode ............................................................... 47
TM
Table 7-9 Display Register – at SMART FAN
III Mode ................................................................ 50
TM
Table 7-10 Relative Register – at SMART FAN
III Control Mode................................................ 51
Table 9-1 The Delays of the FIFO................................................................................................... 93
Table 9-2 FDC Registers............................................................................................................... 103
Table 10-1 Register Summary for UART ...................................................................................... 117
Table 11-1 Pin Descriptions for SPP, EPP, and ECP Modes ....................................................... 124
Table 11-2 EPP Register Addresses ............................................................................................ 124
Table 11-3 Address and Bit Map for SPP and EPP Modes .......................................................... 125
Table 11-4 ECP Mode Description................................................................................................ 128
Table 11-5 ECP Register Addresses ............................................................................................ 129
Table 11-6 Bit Map of the ECP Registers ..................................................................................... 129
Table 12-1 Bit Map of Status Register .......................................................................................... 138
Table 12-2 KBC Command Sets................................................................................................... 138
Table 13-1 Bit Map of Logical Device A, CR[E4h], bits [6:5]......................................................... 145
Table 13-2 Definitions of Mouse Wake-Up Events ....................................................................... 148
Table 13-3 Timing and Voltage Parameters of RSMRST# ........................................................... 148
Table 14-1 SERIRQ Sampling Periods ......................................................................................... 152
Table 16-1 Relative Control Registers of GPIO 25, 26 and 27 that Support Wake-Up Function . 155
Table 16-2 GPIO Register Addresses........................................................................................... 156
Publication Release Date: October 26, 2010
-IX-
Revision 1.7