NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 129

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

DEFAULT
10.2.5 This register is used to control the FIFO functions of the UART
NAME
BIT
BIT
5-4
7
6
5
4
3
2
1
0
BIT
7
6
3
2
1
0
DCD (Data Carrier Detect). This bit is the inverse of the DCD# input and is equivalent to
bit 3 of HCR in Loopback mode.
RI (Ring Indicator). This bit is the inverse of the RI# input and is equivalent to bit 2 of
HCR in Loopback mode.
DSR (Data Set Ready). This bit is the inverse of the DSR# input and is equivalent to bit 0
of HCR in Loopback mode.
CTS (Clear to Send). This bit is the inverse of the CTS# input and is equivalent to bit 1 of
HCR in Loopback mode.
TDCD (DCD# Toggling). This bit indicates that the state of the DCD# pin has changed
after HSR is read by the CPU.
FERI (RI Falling Edge). This bit indicates that the RI# pin has changed from low to high
after HSR is read by the CPU.
TDSR (DSR# Toggling). This bit indicates that the state of the DSR# pin has changed
after HSR is read by the CPU.
TCTS (CTS# Toggling). This bit indicates that the state of the CTS# pin has changed
after HSR is read by the CPU.
MSB (RX Interrupt Active Level).
LSB (RX Interrupt Active Level).
RESERVED.
DMS MODE SELECT. When this bit is set to logic 1, DMA mode changes from mode 0 to
mode 1 if UFR bit 0 = 1.
TRANSMITTER FIFO RESET. Setting this bit to logic 1 resets the TX FIFO counter logic
to its initial state. This bit is automatically cleared afterwards.
RECEIVER FIFO RESET. Setting this bit to logic 1 resets the RX FIFO counter logic to its
initial state. This bit is automatically cleared afterwards.
FIFO ENABLE. This bit enables 16550 (FIFO) mode. This bit should be set to logic 1
before other UFR bits are programmed.
MSB
7
0
LSB
6
0
NA
5
RESERVED
NA
4
DESCRIPTION
DESCRIPTION
SELECT
MODE
These two bits are used to set the active
level of the receiver FIFO interrupt. The
active level is the number of bytes that
must be in the receiver FIFO to generate
an interrupt.
DMA
3
0
-120-
W83627UHG/NCT6627UD
TRANSMITTER
FIFO RESET
2
0
Publication Release Date: October 26, 2010
RECEIVER
RESET
FIFO
1
0
ENABLE
FIFO
0
0
Revision 1.7