NCT6627UD Nuvoton Technology Corporation of America, NCT6627UD Datasheet - Page 62

• Manufacturer Part Number: NCT6627UD
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of NCT6627UD

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(3) One-Time Interrupt Mode
(2) Two-Times Interrupt Mode
In this mode, the SMI# pin can create an interrupt when the current temperature rises above T
current temperature falls below T
interrupt, this mode does not generate additional interrupts, even if the temperature remains above T
the temperature falls below T
subsequent events do not generate interrupts. This is illustrated in the figure above.
In this mode, the SMI# pin can create an interrupt as long as the current temperature exceeds T
Temperature). This interrupt can be reset by reading all the interrupt status registers, or subsequent events
do not generate interrupts. If the interrupt is reset, the SMI# pin continues to create interrupts until the
temperature goes below T
This mode is enabled by setting T
bit 5 to zero.
This mode is enabled by setting T
bit 5 to one.
In this mode, the SMI# pin can create an interrupt when the current temperature rises above T
temperature rises above T
interrupts, even if the temperature remains above T
must be reset by reading all the interrupt status registers, or subsequent events do not generate interrupts.
This is illustrated in the following figure.
127'C
T
SMI#
HYST
T
OI
*
*Interrupt Reset when Interrupt Status Registers are read
*
O
O
. This is illustrated in the figure below.
, however, and generates an interrupt, this mode does not generate additional
HYST
*
. This interrupt must be reset by reading all the interrupt status registers, or
HYST
HYST
HYST
Figure 7-18 SMI Mode of SYSTIN I
. Once the temperature rises above T
(Temperature Hysteresis) lower than T
(Temperature Hysteresis) lower than T
*
O
, until the temperature falls below T
T
HYST
SMI#
-53-
T
OI
W83627UHG/NCT6627UD
Publication Release Date: October 26, 2010
*
O
O
O
, however, and generates an
and setting Bank0 Index 4Ch,
and setting Bank0 Index 4Ch,
*
HYST
. This interrupt
O
or when the
O
Revision 1.7
. Once the
*
O
O
(Over
, until