ADDS-BF533-EZLITE Analog Devices Inc, ADDS-BF533-EZLITE Datasheet - Page 41

• Manufacturer Part Number: ADDS-BF533-EZLITE
• Manufacturer: Analog Devices Inc

Specifications of ADDS-BF533-EZLITE

• Significant Other Parts: ADV7183 Video Decode
• Lead Free Status / Rohs Status: Not Compliant

Timer Cycle Timing
Table 29
input signal is asynchronous in width capture mode and exter­
nal clock mode and has an absolute maximum input frequency
of f
Table 29. Timer Cycle Timing
1
2
Parameter
Timing Characteristics
t
t
Switching Characteristic
t
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
The minimum time for t
WL
WH
HTO
SCLK
Timer Pulse Width Input Low
Timer Pulse Width Input High
Timer Pulse Width Output
/2 MHz.
CLKOUT
(PWM OUTPUT MODE)
EXTERNAL CLOCK MODES)
and
(WIDTH CAPTURE AND
Figure 28
TMRx
TMRx
HTO
is one cycle, and the maximum time for t
describe timer expired operations. The
2
(Measured in SCLK Cycles)
1
1
(Measured in SCLK Cycles)
(Measured in SCLK Cycles)
Figure 28. Timer PWM_OUT Cycle Timing
t
WL
Rev. E | Page 41 of 60 | July 2007
HTO
equals (2
32
–1) cycles.
ADSP-BF531/ADSP-BF532/ADSP-BF533
t
WH
t
HTO
Min
1
1
1
V
DDEXT
Max
(2
= 1.8 V
32
–1)
Min
1
1
1
V
DDEXT
= 2.5 V/3.3 V
Max
(2
32
–1)
Unit
SCLK
SCLK
SCLK