ADDS-BF533-EZLITE Analog Devices Inc, ADDS-BF533-EZLITE Datasheet - Page 38

• Manufacturer Part Number: ADDS-BF533-EZLITE
• Manufacturer: Analog Devices Inc

Specifications of ADDS-BF533-EZLITE

• Significant Other Parts: ADV7183 Video Decode
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port
—Slave Timing
Table 27
Table 27. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
SPICHS
SPICLS
SPICLK
HDS
SPITDS
SDSCI
SSPID
HSPID
DSOE
DSDHI
DDSPID
HDSPID
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISS Not Asserted
Sequential Transfer Delay
SPISS Assertion to First SCK Edge
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
SPISS Assertion to Data Out Active
SPISS Deassertion to Data High Impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
CPHA = 0
and
CPHA = 1
Figure 25
(INPUT)
(INPUT)
(INPUT)
(OUTPUT)
(OUTPUT)
(CPOL = 0)
(CPOL = 1)
SPISS
MOSI
MOSI
(INPUT)
(INPUT)
MISO
MISO
SCK
SCK
describe SPI port slave operations.
t
DSOE
t
DSOE
t
SDSCI
MSB VALID
t
t
t
DDSPID
t
SPICHS
SPICLS
MSB VALID
SSPID
t
Figure 25. Serial Peripheral Interface (SPI) Port—Slave Timing
DDSPID
MSB
t
t
MSB
SPICLS
SPICHS
t
Rev. E | Page 38 of 60 | July 2007
HDSPID
Min
2t
2t
4t
2t
2t
2t
1.6
1.6
0
0
0
0
t
HSPID
LQFP/PBGA Packages
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
V
DDEXT
= 1.8 V
t
SSPID
Max
10
10
10
10
t
LSB VALID
DDSPID
t
t
SPICLK
SSPID
Min
2t
2t
4t
2t
2t
2t
1.6
1.6
0
0
0
0
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
LSB
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
MBGA Package
LSB VALID
V
DDEXT
t
HSPID
= 1.8 V
t
t
DSDHI
HDS
t
LSB
DSDHI
Max
9
9
10
10
t
HSPID
t
SPITDS
Min
2t
2t
4t
2t
2t
2t
1.6
1.6
0
0
0
0
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
V
DDEXT
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
All Packages
= 2.5 V/3.3 V
Max
8
8
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns