NAND01GR3B2CZA6E Micron Technology Inc, NAND01GR3B2CZA6E Datasheet - Page 7

• Manufacturer Part Number: NAND01GR3B2CZA6E
• Manufacturer: Micron Technology Inc

Specifications of NAND01GR3B2CZA6E

• Cell Type: NAND
• Density: 1Gb
• Access Time (max): 25us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Program/erase Volt (typ): 1.7 to 1.95V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.95V
• Word Size: 8b
• Number Of Words: 128M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / Rohs Status: Compliant

NAND01G-B2C
1
Description
The NAND01G-B2C is a 1-Gbit device belonging to the NAND SLC large page family. The
device operates with a 1.8 V or 3 V voltage supply. The size of a page is either 2112 bytes
(2048 + 64 spare) or 1056 words (1024 + 32 spare) depending on whether the device has a
x8 or x16 bus width.
The address lines are multiplexed with the data input/output signals on a multiplexed x8 or
x16 input/output bus. This interface reduces the pin count and makes it possible to migrate
to other densities without changing the footprint.
Each block can be programmed and erased up to 100,000 cycles (with ECC on). To extend
the lifetime of NAND flash devices, the implementation of an error correction code (ECC) is
mandatory.
The devices feature a write protect pin that allows performing hardware protection against
program and erase operations.
The devices feature an open-drain ready/busy output that can be used to identify if the
program/erase/read (P/E/R) controller is currently active. The use of an open-drain output
allows the ready/busy pins from several memories to be connected to a single pull-up
resistor.
A Copy Back Program command is available to optimize the management of defective
blocks. When a page program operation fails, the data can be programmed in another page
without having to resend the data to be programmed.
The cache read feature is also implemented according to ONFI 1.0 specification.
All devices have the chip enable don’t care feature, which allows the bus to be shared
among several memories active at the same time, as chip enable transitions during the
latency time do not stop the read operation. Program and erase operations can never be
interrupted by chip enable transitions.
The devices are available in the following packages:
and come with three security features:
These security features are subject to an NDA (non-disclosure agreement) and are,
therefore, not described in the datasheet. For more details about them, refer to the nearest
Numonyx sales office.
For information on how to order these options refer to
scheme. Devices are shipped from the factory with block 0 always valid and the memory
content bits, in valid blocks, erased to ’1’.
See
Table 2: Product
TSOP48 (12 x 20 mm)
VFBGA63 (9 x 11 x 1.05 mm, 0.8 mm pitch)
VFBGA153 (8 x 9 x 0.9 mm, 0.5 mm pitch)
OTP (one time programmable) area, which is a restricted access area where sensitive
data/code can be stored permanently.
Serial number (unique identifier), which allows the devices to be uniquely identified.
Non-volatile protection to lock sensible data permanently. For more details of this
option contact your nearest Numonyx sales office.
description, for all the devices available in the family.
Table 28: Ordering information
Description
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