NAND01GR3B2CZA6E Micron Technology Inc, NAND01GR3B2CZA6E Datasheet - Page 32

• Manufacturer Part Number: NAND01GR3B2CZA6E
• Manufacturer: Micron Technology Inc

Specifications of NAND01GR3B2CZA6E

• Cell Type: NAND
• Density: 1Gb
• Access Time (max): 25us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Program/erase Volt (typ): 1.7 to 1.95V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.95V
• Word Size: 8b
• Number Of Words: 128M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / Rohs Status: Compliant

Device operations
6.7.3
6.7.4
6.7.5
Table 11.
32/67
SR4, SR3,
SR2, SR1
SR7
SR6
SR5
SR0
Bit
P/E/R controller bit (SR5)
The program/erase/read controller bit indicates whether the P/E/R controller is active or
inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is
busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready).
Error bit (SR0)
The error bit is used to identify if any errors have been detected by the P/E/R controller. The
error bit is set to ’1’ when a program or erase operation has failed to write the correct data to
the memory. If the error bit is set to ‘0’ the operation has completed successfully.
SR4, SR3, SR2, and SR1 are reserved
Status register bits
Program/ erase/ read
Program/ erase/ read
Cache ready/busy
Write protection
Generic error
Reserved
controller
controller
Name
Logic level
Don’t care
‘1’
‘0’
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
Not protected
Protected
P/E/R C inactive, device ready
P/E/R C active, device busy
Cache register ready (cache operation only)
Cache register busy (cache operation only)
P/E/R C inactive, device ready
P/E/R C active, device busy
Error – operation failed
No error – operation successful
Definition
NAND01G-B2C