NAND01GR3B2CZA6E Micron Technology Inc, NAND01GR3B2CZA6E Datasheet - Page 17

• Manufacturer Part Number: NAND01GR3B2CZA6E
• Manufacturer: Micron Technology Inc

Specifications of NAND01GR3B2CZA6E

• Cell Type: NAND
• Density: 1Gb
• Access Time (max): 25us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Program/erase Volt (typ): 1.7 to 1.95V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.95V
• Word Size: 8b
• Number Of Words: 128M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / Rohs Status: Compliant

NAND01G-B2C
4
4.1
4.2
4.3
4.4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see
Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
Command input
Command input bus operations are used to give commands to the memory. Commands are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal. For commands that start a modify operation (write/erase) the Write Protect pin must
be High.
Only I/O0 to I/O7 are used to input commands.
See
Address input
Address input bus operations are used to input the memory addresses. Four bus cycles are
required to input the addresses for 1-Gbit devices (refer to
insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. For commands that start a modify operation (write/erase)
the Write Protect pin must be High. Only I/O0 to I/O7 are used to input addresses.
See
Data input
Data input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low, Read Enable, and Write Protect is High. The data is latched on the
rising edge of the Write Enable signal. The data is input sequentially using the Write Enable
signal.
See
Data output
Data output bus operations are used to read: the data in the memory array, the status
register, the electronic signature and the unique identifier.
Figure 21
Figure 22
Figure 23
and
and
and
Table 5: Bus
Table 24
Table 24
Table 24
for details of the timings requirements.
for details of the timings requirements.
and
operations, for a summary.
Table 25
for details of the timings requirements.
Table 6
and
Table
Bus operations
7, Address
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