MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 253

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.38.3.2.11
Read: Anytime
Write: Only in Special Mode
4.38.3.2.12
Freescale Semiconductor
cpmu_test_clk_
cpmu_test_clk_
osc_lcp_monito
osc_lcp_extsq
0x003E
pfd_force_en
pfd_force_up
pfd_force_up
Reset
w_enable
r_disable
W
sel[1:0]
R
Field
5, 4
en
7
6
3
2
1
0
pfd_force_e
Phase Detector Force Enable Bit— This bit breaks the PLL feedback loop and allows force of phase detector via
pfd_force_up or pfd_force_down bit or cpmu_test_xfc pin or fc_force_en.
0 Normal functionality of Phase Detector using REFCLK and FBCLK.
1 Phase detector de-connected from REFCLK and FBCLK (PLL loop open).
CPMU test clock enable Bit— This bits routes the clock selected by cpmu_test_clk_sel[1:0] to external pin cpmu_test_clk.
0 CPMU test clock not observable.
1 CPMU test clock observable at external pin.
or characterization purposes.
00 = IRCCLK, 01=OSCCLK, 10=VCOCLK, 11=VCOCLK_DIV4.
Oscillator clock monitor disable Bit — to disable the clock monitor in special single chip mode.
0 Clock monitor always enabled with OSCE=1.
1 Clock monitor disabled regardless of OSCE Bit.
Oscillator external square wave enable Bit — Drives directly osc_lcp_extsqw_enable input of OSCLCP hardmacro.
Phase Detector Force Up Bit — If pfd_force_en=1, this bits force the PLL charge pump to drive the internal filter voltage down,
that is VCOCLK frequency goes up. Using this test feature make sure that only one source is driving the internal filter node
(FC). So for this case write xfc_en=fc_force_en=pfd_force_down=0.
0 No effect.
1 If pfd_force_en=1 then the charge pump continuously drives internal filter node down.
Phase Detector Force Down Bit — If pfd_force_en=1, this bits force the PLL charge pump to drive the internal filter voltage
up, that is VCOCLK frequency goes down. Using this test feature make sure that only one source is driving the internal filter
node (FC). So for this case write xfc_en=fc_force_en=pfd_force_up=0.
0 No effect.
1 If pfd_force_en=1 then the charge pump continuously drives internal filter node up.
CPMU test clock select Bits— These bits select the CPMU test clock to be observed on external pin cpmu_test_clk for test
n
7
0
0
Reserved Register CPMUTEST1
This reserved register is designed for factory test purposes only, and is not intended for
general user access. Writing to this register when in Special Mode can alter the S12CPMU’s
functionality.
Reserved Register CPMUFMCS
cpmu_test_c
lk_en
6
0
= Unimplemented or Reserved
0
Table 361. Reserved Register (CPMUTEST1)
cpmu_test_c
Table 362. CPMUTEST1 Field Descriptions
lk_sel[1]
MM912_634 Advance Information, Rev. 4.0
5
0
0
cpmu_test_c
lk_sel[0]
NOTE
4
0
0
Description
nitor_disable
osc_lcp_mo
3
0
0
osc_lcp_exts
qw_enable
2
0
0
pfd_force_u
p
1
0
0
pfd_force_d
own
0
0
0
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