MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 127

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Note:
4.19.3.3.10
119.
4.19.3.3.11
Freescale Semiconductor
Offset
Note:
120.
Offset
Reset
Reset
W
R
W
R
PR[2:0]
(119)
C[3-0]I
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
TCRE
Field
Field
(120)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
TOI
3-0
3-0
7
3
0xCA
0xCB
7
0
0
TOI
Input Capture/Output Compare Interrupt Enable.
Timer Overflow Interrupt Enable
TCRE — Timer Counter Reset Enable
Timer Prescaler Select
These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in
7
0
Timer Interrupt Enable Register (TIE)
Timer System Control Register 2 (TSCR2)
This mode of operation is similar to an up-counting modulus counter.
If register TC3 = $0000 and TCRE = 1, the timer counter register (TCNT) will stay at $0000
continuously. If register TC3 = $FFFF and TCRE = 1, TOF will not be set when the timer
counter register (TCNT) is reset from $FFFF to $0000.
The newly selected prescale factor will not take effect until the next synchronized edge,
where all prescale counter stages equal zero.
1 = Enables corresponding Interrupt flag (CnF of TFLG1 register) to cause a hardware interrupt
0 = Disables corresponding Interrupt flag (CnF of TFLG1 register) from causing a hardware interrupt
1 = Hardware interrupt requested when TOF flag set in TFLG2 register.
0 = Hardware Interrupt request inhibited.
1 = Enables Timer Counter reset by a successful output compare on channel 3
0 = Inhibits Timer Counter reset and counter continues to run.
6
0
0
6
0
0
Table 184. Timer System Control Register 2 (TSCR2)
Table 182. Timer Interrupt Enable Register (TIE)
Table 183. TIE - Register Field Descriptions
Table 185. TIE - Register Field Descriptions
MM912_634 Advance Information, Rev. 4.0
5
0
0
5
0
0
NOTE
4
0
0
4
0
0
Description
Description
TCRE
C3I
3
0
3
0
Basic Timer Module - TIM (TIM16B4C)
PR2
C2I
0
2
0
2
PR1
C1I
1
0
1
0
Access: User read/write
Access: User read/write
Table
186.
PR0
C0I
0
0
0
0
127