MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 210

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 303
is set since the match occurs based on the tagged opcode reaching the execution stage of the instruction queue.
Freescale Semiconductor
(Comparator A)
(Comparators
(Comparators
A and B)
A and B)
COMPE
Field
RWE
BRK
NDB
SZE
TAG
RW
SZ
7
6
5
4
3
2
1
0
shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the corresponding TAG bit
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the associated
comparator. This bit is ignored if the TAG bit in the same register is set.
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the associated
comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
Tag Select — This bit controls whether the comparator match has immediate effect, causing an immediate state sequencer
transition or tag the opcode at the matched address. Tagged opcodes trigger only if they reach the execution stage of the
instruction queue.
Break — This bit controls whether a comparator match terminates a debug session immediately, independent of state
sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled using the DBGC1 bit
DBGBRK.
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated
comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same register is set.
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated
comparator.This bit is ignored if the TAG bit in the same register is set
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator register value
or when the data bus differs from the register value. This bit is ignored if the TAG bit in the same register is set. This bit is
only available for comparator A.
Determines if comparator is enabled
RWE Bit
0
1
0
1
0
1
0
1
if active, is terminated and the module disarmed.
0
0
1
0
1
0
1
0
0
1
1
1
1
Word/Byte access size is not used in comparison
Word/Byte access size is used in comparison
Word access size is compared
Byte access size is compared
Allow state sequencer transition immediately on match
On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition
The debug session termination is dependent upon the state sequencer and trigger conditions.
A match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing,
Write cycle is matched1
Read/Write is not used in comparison
Read/Write is used in comparison
Match on data bus equivalence to comparator register contents
Match on data bus difference to comparator register contents
The comparator is not enabled
The comparator is enabled
RW Bit
Table 303. Read or Write Comparison Logic Table
0
0
1
1
x
x
Table 302. DBGXCTL Field Descriptions
MM912_634 Advance Information, Rev. 4.0
Read cycle is matched
RW Signal
0
1
0
1
0
1
Description
RW not used in comparison
RW not used in comparison
Read data bus
Write data bus
Comment
No match
No match
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