MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 176

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.29.5.1.1
The arbitration scheme allows only one master to be connected to a target at any given time. The following rules apply when
prioritizing accesses from different masters to the same target bus:
4.29.5.2
The MMC does not generate any interrupts.
4.29.6
4.29.6.1
CALL and RTC instructions are uninterruptable CPU instructions that automate page switching in the program page window. The
CALL instruction is similar to the JSR instruction, but the subroutine that is called can be located anywhere in the local address
space or in any Flash or ROM page visible through the program page window. The CALL instruction calculates and stacks a
return address, stacks the current PPAGE value and writes a new instruction-supplied value to the PPAGE register. The PPAGE
value controls which of the 256 possible pages is visible through the 16 kbyte program page window in the 64 kbyte local CPU
memory map. Execution then begins at the address of the called subroutine.
During the execution of the CALL instruction, the CPU performs the following steps:
This sequence is uninterruptable. There is no need to inhibit interrupts during the CALL instruction execution. A CALL instruction
can be performed from any address to any other address in the local CPU memory space.
The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing mode variations
(except indexed-indirect modes) the new page value is provided by an immediate operand in the instruction. In indexed-indirect
variations of the CALL instruction a pointer specifies memory locations where the new page value and the address of the called
subroutine are stored. Using indirect addressing for both the new page value and the address within the page allows usage of
values calculated at run time rather than immediate values that must be known at the time of assembly.
Freescale Semiconductor
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CPU12 always has priority over BDM.
BDM has priority over CPU12 when its access is stalled for more than 128 cycles. In the later case the CPU will be
stalled after finishing the current operation and the BDM will gain access to the bus.
Writes the current PPAGE value into an internal temporary register and writes the new instruction-supplied PPAGE
value into the PPAGE register
Calculates the address of the next instruction after the CALL instruction (the return address) and pushes this 16-bit value
onto the stack
Pushes the temporarily stored PPAGE value onto the stack
Calculates the effective address of the subroutine, refills the queue and begins execution at the new address
Initialization/Application Information
Interrupts
CALL and RTC Instructions
Master Bus Prioritization regarding Access Conflicts on Target Buses
P-Flash
DBG
D-Flash
MM912_634 Advance Information, Rev. 4.0
Figure 54. S12I Platform
MMC “Crossbar Switch”
resources
CPU
BDM
XBUS0
S12X0
SRAM
S12X1
Peripherals
BDM
IPBI
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