MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 206

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The priorities described in
followed by the match on the lower channel number (0,1,2). Thus with SC[3:0]=1101 a simultaneous match0/match1 transitions
to final state.
4.32.3.2.7.2
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the targeted next state whilst in
State2. The matches refer to the match channels of the comparator match control logic as depicted in
in
comparator enable bit in the associated DBGXCTL control register.
Freescale Semiconductor
Address: 0x0027
Reset
Section 4.32.3.2.8.1, “Debug Comparator Control Register
SC[3:0]
SC[3:0]
0100
0101
1000
1001
1010
0000
0001
0010
0011
0110
0111
1011
1100
1101
1110
SC[3:0]
1111
W
R
Field
3–0
These bits select the targeted next state whilst in State2, based upon the match event.
7
0
0
Debug State Control Register 2 (DBGSCR2)
Table 323
6
0
0
= Unimplemented or Reserved
Table 291. Debug State Control Register 2 (DBGSCR2)
Table 293. State2 —Sequencer Next State Selection
dictate that in the case of simultaneous matches, a match leading to final state has priority
Table 290. State1 Sequencer Next State Selection
Table 292. DBGSCR2 Field Descriptions
Either Match0 or Match2 to Final State........Match1 to State2
MM912_634 Advance Information, Rev. 4.0
Description (Unspecified matches have no effect)
Description (Unspecified matches have no effect)
5
0
0
Match1 to State3.........Match0 to Final State
Match0 to State1....... Match2 to State3.
Match0 to State2....... Match1 to State3
Match0 to State2....... Match2 to State3
Either Match0 or Match1 to State2
4
0
0
(DBGXCTL). Comparators must be enabled by setting the
Match1 to State2
Match1 to State3
Match2 to State3
Match0 to State3
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SC3
3
0
SC2
2
0
Figure 65
SC1
1
0
and described
SC0
0
0
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