MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 190

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.31.4.6
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which
selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
BDM.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate
the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most
significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges
from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that
there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Since R-C rise time could
be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The
source of this speedup pulse is the host for transmit cases and the target for receive cases.
The timing for host-to-target is shown in
the host drives the BKGD pin low to generate a falling edge. Since the host and target are operating from separate clocks, it can
take the target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of
the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle
earlier. Synchronization between the host and target is established in this manner at the start of every bit time.
Figure 58
is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target
recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD
pin. Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a
logic 1 transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals.
The receive cases are more complicated.
asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived
start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target
clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles
after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.
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This clock will be referred to as the target clock in the following explanation.
Start of Bit Time
(Target MCU)
BDM Clock
Transmit 1
Transmit 0
Perceived
shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host
Host
Host
BDM Serial Interface
Synchronization
Uncertainty
Figure 58. BDM Host-to-Target Serial Bit Timing
Figure 58
Figure 59
MM912_634 Advance Information, Rev. 4.0
and that of target-to-host in
10 Cycles
shows the host receiving a logic 1 from the target system. Since the host is
Target Senses Bit
Figure 59
and
Figure
60. All four cases begin when
Next Bit
Earliest
Start of
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