MM912H634CM1AE Freescale Semiconductor, MM912H634CM1AE Datasheet - Page 227

• Manufacturer Part Number: MM912H634CM1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2 comparators, State 3
allowing a M0 to return to state 2, whilst a M2 leads to final state as shown.
The advantage of using only 2 channels is that now range comparisons can be included (channel0)
This however violates the S12SDBGV1 specification, which states that a match leading to final state always has priority in case
of a simultaneous match, whilst priority is also given to the lowest channel number. For S12SDBG the corresponding CPU priority
decoder is removed to support this, such that on simultaneous taghits, taghits pointing to final state have highest priority. If no
taghit points to final state then the lowest channel number has priority. Thus with the above encoding from State3, the CPU and
DBG would break on a simultaneous M0/M2.
4.32.5.6
Trigger if following event A, event C precedes event B. i.e. the expected execution flow is A->B->C.
Scenario 5 is possible with the S12SDBGV1 SCR encoding
4.32.5.7
Trigger if event A occurs twice in succession before any of 2 other events (BC) occurs. This scenario is not possible using the
S12SDBGV1 SCR encoding. S12SDBGV2 includes additions shown in red. The change in SCR1 encoding also has the
advantage that a State1->State3 transition using M0 is now possible. This is advantageous because range and data bus
comparisons use channel0 only.
4.32.5.8
Trigger when a series of 3 events is executed out of order. Specifying the event order as M1,M2,M0 to run in loops (120120120).
Any deviation from that order should trigger. This scenario is not possible using the S12SDBGV1 SCR encoding because OR
possibilities are very limited in the channel encoding. By adding OR forks as shown in red this scenario is possible.
Freescale Semiconductor
Scenario 5
Scenario 6
Scenario 7
SCR3=1110
SCR1=0110
SCR1=0011
State1
SCR1=1001
State1
Figure 75. Scenario 4b (with 2 comparators)
MM912_634 Advance Information, Rev. 4.0
M2
State1
State 3
M1
M2
M0
Figure 76. Scenario 5
Figure 77. Scenario 6
M12
SCR2=0110
State2
SCR3=1010
M0
M0
State3
M2
M2
M0
Final State
M0
State2
M01
Final State
Final State
SCR2=1100
M1 disabled in
range mode
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