PIC18F6585-I/PT Microchip Technology Inc., PIC18F6585-I/PT Datasheet - Page 432

• Manufacturer Part Number: PIC18F6585-I/PT
• Description: 64 PIN, 48 KB FLASH, 3328 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6585-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 48K Bytes
• Ram Size: 3.3K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6585/8585/6680/8680
TABLE 27-8:
FIGURE 27-8:
DS30491C-page 430
10
11
12
13
14
15
16
17
18
18A
19
20
20A
21
21A
22†
23†
24†
Note 1:
Param.
AD<15:0>
A<19:16>
No.
OSC1
BA0
ALE
†
OE
CE
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OS
OS
CK
CK
CK
CK
OS
OS
IO
IO
IO
IO
INP
RBP
RCP
Symbol
These parameters are asynchronous events not related to any internal clock edges.
Measurements are taken in RC mode, where CLKO output is 4 x T
V2
V2
R
F
R
F
L2
H2
H2
H2
H2
H2
CK
OS
IO
IO
CK
CK
IO
IO
V
H Port In Valid before CLKO
I
V OSC1
I
H Port Input Valid to OSC1
L OSC1
H OSC1
CLKO AND I/O TIMING REQUIREMENTS
CLKO Rise Time
CLKO Fall Time
CLKO
Port In Hold after CLKO
OSC1
Input Invalid
(I/O in hold time)
Port Output Rise Time
Port Output Fall Time
INT pin High or Low Time
RB7:RB4 Change INT High or Low Time
RC7:RC4 Change INT High or Low Time
Q1
PROGRAM MEMORY READ TIMING DIAGRAM
to CLKO
to CLKO
to Port Out Valid
(Q1 cycle) to Port Out Valid
(Q2 cycle) to Port
164
Address
Address
150
151
Characteristic
171
171A
Q2
(I/O in setup time)
PIC18FXX8X
PIC18LFXX8X
PIC18FXX8X
PIC18LFXX8X
PIC18FXX8X
PIC18LFXX8X
167
155
160
Q3
166
168
169
0.25 T
165
Min
100
200
T
T
Data from External
20
—
—
—
—
—
—
—
—
—
—
CY
0
0
CY
CY
OSC
Q4
+ 25
162
.
163
Typ
75
75
35
35
50
10
10
—
—
—
—
—
—
—
—
—
—
161
0.5 T
 2004 Microchip Technology Inc.
Q1
Max
200
200
100
100
150
CY
25
60
25
60
—
—
—
—
—
—
—
+ 20
Units Conditions
Address
Address
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Q2
(1)
(1)
(1)
(1)
(1)
(1)
(1)