PIC18F6585-I/PT Microchip Technology Inc., PIC18F6585-I/PT Datasheet - Page 245

• Manufacturer Part Number: PIC18F6585-I/PT
• Description: 64 PIN, 48 KB FLASH, 3328 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6585-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 48K Bytes
• Ram Size: 3.3K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

18.2.5
The enhanced USART module has the capability of
sending the special break character sequences that
are required by the LIN bus standard. The break char-
acter transmit consists of a Start bit, followed by twelve
‘0’ bits and a Stop bit. The frame break character is sent
whenever the SENDB and TXEN bits (TXSTA<3> and
TXSTA<5>) are set while the Transmit Shift register is
loaded with data. Note that the value of data written to
TXREG will be ignored and all ‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the break character (typically, the sync
character in the LIN specification).
Note that the data value written to the TXREG for the
break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 18-9 for the timing of the break
character sequence.
FIGURE 18-9:
 2004 Microchip Technology Inc.
Reg. Empty Flag)
Reg. Empty Flag)
Reg. Empty Flag)
Write to TXREG
(Transmit Buffer
(Transmit Shift
(Transmit Shift
BRG Output
(Shift Clock)
TRMT bit
TX (pin)
TXIF bit
SENDB
BREAK CHARACTER SEQUENCE
SEND BREAK CHARACTER SEQUENCE
Dummy Write
SENDB Sampled Here
Start Bit
PIC18F6585/8585/6680/8680
Bit 0
Bit 1
Break
18.2.5.1
The following sequence will send a message frame
header made up of a break, followed by an auto-baud
sync byte. This sequence is typical of a LIN bus master.
1.
2.
3.
4.
5.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
18.2.6
The enhanced USART module can receive a break
character in two ways.
The first method forces the configuration of the baud
rate at a frequency of 9/13 the typical speed. This
allows for the Stop bit transition to be at the correct
sampling location (13 bits for break versus Start bit and
8 data bits for typical data).
The second method uses the auto-wake-up feature
described in Section 18.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
USART will sample the next two transitions on RX/DT,
cause an RCIF interrupt, and receive the next data byte
followed by another interrupt.
Note that following a break character, the user will typ-
ically want to enable the auto-baud rate detect feature.
For both methods, the user can set the ABD bit once
the TXIF interrupt is observed.
Configure the USART for the desired mode.
Set the TXEN and SENDB bits to set up the
break character.
Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
Write ‘55h’ to TXREG to load the sync character
into the transmit FIFO buffer.
After the break has been sent, the SENDB bit is
reset by hardware. The sync character now
transmits in the preconfigured mode.
RECEIVING A BREAK CHARACTER
Break and Sync Transmit Sequence
Bit 11
Auto-Cleared
Stop Bit
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