PIC18F6585-I/PT Microchip Technology Inc., PIC18F6585-I/PT Datasheet - Page 31

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PIC18F6585-I/PT

Manufacturer Part Number
PIC18F6585-I/PT
Description
64 PIN, 48 KB FLASH, 3328 RAM, 52 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F6585-I/PT

A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
53
Interface
CAN/I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
64-pin TQFP
Programmable Memory
48K Bytes
Ram Size
3.3K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F6585-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F6585-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
If the main oscillator is configured for HS mode with
PLL active, an oscillator start-up time (T
additional PLL time-out (T
out is typically 2 ms and allows the PLL to lock to the
main oscillator frequency. A timing diagram, indicating
the transition from the Timer1 oscillator to the main
oscillator for HS-PLL mode, is shown in Figure 2-10.
FIGURE 2-10:
FIGURE 2-11:
 2004 Microchip Technology Inc.
Program Counter
Program Counter
Note:
Internal System
Internal System
(OSCCON<0>)
(OSCCON<0>)
PLL Clock
PLL Clock
T1OSI
T1OSI
OSC1
OSC1
Clock
Clock
Input
T
Input
SCS
SCS
OST
= 1024 T
Q4
PC
Q4
PC
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(HS WITH PLL ACTIVE, SCS1 = 1)
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(EC WITH PLL ACTIVE, SCS1 = 1)
OSC
PLL
(drawing not to scale).
Q1
Q1
) will occur. The PLL time-
T
OST
T
PLL
OST
T
PLL
PIC18F6585/8585/6680/8680
) plus an
T
PC + 2
T
PC + 2
OSC
OSC
1
1
If the main oscillator is configured for EC mode with PLL
active, only the PLL time-out (T
time-out is typically 2 ms and allows the PLL to lock to
the main oscillator frequency. A timing diagram, indicat-
ing the transition from the Timer1 oscillator to the main
oscillator for EC with PLL active, is shown in Figure 2-11.
2
2
3
3
T
T
SCS
SCS
T
4
T
4
T
T
1
1
P
P
5
5
6
6
7
7
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
8
8
PLL
) will occur. The PLL
DS30491C-page 29
Q1 Q2
Q1 Q2
PC + 4
PC + 4
Q3
Q3
Q4
Q4

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