PIC18F6585-I/PT Microchip Technology Inc., PIC18F6585-I/PT Datasheet - Page 133

• Manufacturer Part Number: PIC18F6585-I/PT
• Description: 64 PIN, 48 KB FLASH, 3328 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6585-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 48K Bytes
• Ram Size: 3.3K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

10.3
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory mapped.
Read-modify-write operations on the LATC register read
and write the latched output value for PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.
FIGURE 10-8:
 2004 Microchip Technology Inc.
Note:
RD LATC
Data Bus
RD TRISC
Peripheral Output
Enable
PORTC/Peripheral Out Select
Peripheral Data Out
RD PORTC
WR LATC
WR PORTC
WR TRISC
Peripheral Data In
Note 1: I/O pins have diode protection to V
PORTC, TRISC and LATC
Registers
(2)
On a Power-on Reset, these pins are
configured as digital inputs.
2: Peripheral output enable is only active if peripheral select is active.
or
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
Q
Q
PIC18F6585/8585/6680/8680
DD
Override
and V
TRIS
Logic
0
1
Q
SS
.
EN
D
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register
without concern due to peripheral overrides.
RC1 is normally configured by configuration bit,
CCP2MX, as the default peripheral pin of the CCP2
module (default/erased state, CCP2MX = 1).
EXAMPLE 10-3:
CLRF
CLRF
MOVLW
MOVWF
Schmitt
Trigger
V
N
P
V
DD
SS
PORTC
LATC
0CFh
TRISC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
Pin
I/O pin
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
INITIALIZING PORTC
(1)
Override
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
TRIS OVERRIDE
DS30491C-page 131
Xmit, Sync Clock
Timer1/Timer3,
Timer1 Osc for
Timer1 Osc for
Timer1/Timer3
USART Async
SPI Data Out
USART Sync
Master Clock
I
2
Peripheral
CCP2 I/O
CCP1 I/O
C Data Out
Data Out
SPI/I
2
C