PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 45

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.2.1.2
A 2x32-byte FIFO buffer (receive pools) is provided in the receive direction.
The control of the data transfer between the CPU and the IPAC is handled via interrupts.
There are two different interrupt indications concerned with the reception of data:
– RPF (Receive Pool Full) interrupt, indicating that a 32-byte block of data can be read
– RME (Receive Message End) interrupt, indicating that the reception of one message
is stored in the RFIFOD.
Depending on the message transfer mode the address and control fields of received
frames are processed and stored in the receive FIFO or in special registers as depicted
in figure 15.
The organization of the RFIFOD is such that, in the case of short ( 32 bytes),
successive messages, up to two messages with all additional information can be stored.
The contents of the RFIFOD would be, for example, as shown in figure 14.
Figure 14
Semiconductor Group
from the RFIFOD and the received message is not yet complete.
is completed, i.e. either
• one message
• the last part of a message
Reception of Frames
Contents of RFIFOD (short message)
32 bytes, or
31
31
0
0
(
( < _
Message 2
Message
<
_
RFIFOD
Receive
Receive
32
32
32 bytes
bytes)
bytes)
1
45
Interrupts in
Wait Line
ITD09622
RME
RME
Functional Description
PSB 2115
PSF 2115
11.97