PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 218

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.2
4.2.1
RFIFOB
Interrupt Controlled Data Transfer (Interrupt Mode, selected by XBCH:DMA=0):
Up to 64 bytes of receive data can be read from the RFIFOB following an RPF or an RME
interrupt.
RPF Interrupt: Exactly 64 bytes to be read.
RME Interrupt: Number of bytes to be determined by reading the RBCLB, RBCHB
registers.
Although the address range covers only 32 byte (similar to HSCX-TE) the FIFO depth is
64 byte as the read address does not need to be reprogrammed. Addresses within the
address space of the FIFO’s are interpreted equally, i.e. the actual data byte can be
accessed with any address within the valid scope.
DMA Controlled Data Transfer (DMA Mode, selected by XBCH:DMA=1):
If the RFIFOB contains 64 bytes, the IPAC autonomously requests a block data transfer
by activating the DRQRA/B-line until the 63rd read cycle is finished. This forces the
DMA-controller to continuously perform bus cycles until 64 bytes are transferred from the
IPAC to the system memory (DMA controller mode: demand transfer, level triggered).
If the RFIFOB contains less than 64 bytes (one short frame or the last bytes of a long
frame) the IPAC requests a block data transfer depending on the contents of the RFIFOB
according to the following table:
RFIFOB Contents (bytes)
(1), 2, 3
4 - 7
8 - 15
16 - 31
32 - 64
Additionally an RME interrupt is issued after the last byte has been transferred. As a
result, the DMA-controller may transfer more bytes than actually valid in the current
Semiconductor Group
7
B-Channel Registers
RFIFOB - Receive FIFO B-Channel (Read))
DMA Transfer (bytes)
4
8
16
32
64
Receive data
218
Detailed Register Description
0
(00-1F/40-5F)
PSB 2115
PSF 2115
11.97