PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 130

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

The microprocessor may either enforce a "1" (idle) in MR, MX by setting the control bit
MRC1, 0 or MXC1, 0 to "0" (MONITOR Control Register MOCR), or enable the control
of these bits internally by the IPAC according to the MONITOR channel protocol. Thus,
before a data exchange can begin, the control bit MRC(1, 0) or MXC(1, 0) should be set
to "1" by the microprocessor.
The MONITOR channel protocol is illustrated in figure 63. Since the protocol is identical
in MONITOR channel 0 and MONITOR channel 1 (available in TE mode only), the index
0 or 1 has been left out in the illustration.
The relevant status bits are:
In addition, the status bit:
MONITOR Channel Active MAC (MAC0, MAC1)
indicates whether a transmission is in progress (Register: STARD).
Semiconductor Group
for the reception of MONITOR data, and
for the transmission of MONITOR data (Register: MOSR)
MONITOR Channel Data Received MDR (MDR0, MDR1)
MONITOR Channel End of Reception MER (MER0, MER1)
MONITOR Channel Data Acknowledged MDA (MDA0, MDA1)
MONITOR Channel Data Abort MAB (MAB0, MAB1)
130
Functional Description
PSB 2115
PSF 2115
11.97