PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 264

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

SC1 ... Synchronous Transfer 1 Completed
After a SIN interrupt the processor has to acknowledge the interrupt by setting the SC1
bit before the middle of the IOM frame, if the interrupt was originated from a Synchronous
Transfer 1 (ST1).
Otherwise a SOV interrupt (EXIRD register) will be generated.
SC0 ... Synchronous Transfer 0 Completed
After a SIN interrupt the processor has to acknowledge the interrupt by setting the SC0
bit before the end of the IOM frame, if the interrupt was originated from a Synchronous
Transfer 0 (ST0).
Otherwise a SOV interrupt (EXIRD register) will be generated.
Note: ST0/1 and SC0/1 are useful for synchronizing processor accesses and receive/
4.3.34
Value after reset: (not defined)
B1CR
Used only in terminal mode.
Contains the value received in IOM-channel B1, if programmed
(cf. C1C1, C1C0, SPCR-register).
4.3.35
Value after reset: (not defined)
B2CR
Used only in terminal mode.
Contains the value received in the IOM-channel B2, if programmed
(cf. C2C1, C2C0, SPCR-register).
Semiconductor Group
transmit operations.
B1CR - B1 Channel Register (Read)
7
B2CR - B2 Channel Register (Read)
7
264
Detailed Register Description
0
0
PSB 2115
PSF 2115
11.97
(B7)
(B8)