PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 265

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
4.3.36
Value after reset: 0000xxx0
ADF1
WTC1, 2 ... Watchdog Timer Control 1, 2
After the watchdog timer mode has been selected (STCR:TSF = CIX0:RSS = 1) the
watchdog timer is started.
During every time period of 128 ms the processor has to program the WTC1- and WTC2-
bit in the following sequence:
to reset and restart the watchdog timer.
If not, the timer expires and a WOV-interrupt (EXIRD) together with a reset pulse is
generated.
CI1E ... C/I-channel 1 interrupt enable
Interrupt generation ISTAD:CIC of CIR0:CIC1 is enabled (1) or masked (0).
CSEL2-0 ... IOM-2 Channel Select (in LT modes only)
Select one IOM-channel out of 8, where the IPAC is to receive/transmit B-Channel data.
“000” channel 0 (first channel in IOM-frame)
“001” channel 1
...
“111” channel 7 (last channel in IOM-frame)
The reset value for CSEL2-0 is determined by the pins CH2-0 strapped to VDD or VSS.
After reset the selected channel can be reconfigured by the host and the setting of pins
CH2-0 has no further effect.
WTC1 WTC2 CI1E
ADF1 - Additional Feature Register 1 (Write)
7
1.
2.
WTC1
1
0
2
0
WTC2
0
1
265
CSEL2 CSEL1 CSEL0
Detailed Register Description
0
ITF
PSB 2115
PSF 2115
11.97
(B8)