PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 108

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PSB 2115
PSF 2115
Functional Description
2.6.6
FIFO Structure for B-Channels
In both transmit and receive direction 128 byte deep FIFO’s are provided for the
intermediate storage of B-Channel data between the serial interface and the CPU
interface. The FIFO’s are divided into two halves of 64 bytes, where only one half is
accessible to the CPU at any time.
The organization of the Receive FIFO (RFIFOB) is such, that in the case of a frame at
most 128 bytes long, the whole frame may be stored in the RFIFOB. After the first 64
bytes have been received, the IPAC prompts to read the 64 byte block by means of
interrupt or DMA request (RPF interrupt or activation of DRQR line). This block remains
in the RFIFOB until a confirmation is given to the IPAC acknowledging the transfer of the
data block. This confirmation is either a RMC (Receive Message Complete) command
via the CMDRB register in Interrupt Mode or is implicitely achieved in DMA mode after
64 byte have been read from the RFIFOB. As a result, it’s possible to read out the data
block any number of times until the RMC command is issued.
The configuration of the RFIFO prior to and after acknowledgment is shown in figure 46.
2115_1
Figure 46
Configuration of RFIFOB (Long Frames)
Semiconductor Group
108
11.97