PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 188

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

In LT-T and LT-S applications the IOM interface should be kept active, i.e. the clock
DCL and the frame sync FSC (inputs) should always be supplied by the system.
In TE applications the IOM-2 interface can be switched off in the inactive state,
reducing power consumption to a minimum. In this deactivated state the clock line is low
and the data lines are high.
In TE mode the IOM-2 interface can be kept active while the S interface is deactivated
by setting the CFS bit to "0" (CONF register). This is the case after a hardware reset. If
the IOM-2 interface should be switched off while the S interface is deactivated, the CFS
bit should be set to "1". In this case the internal oscillator is disabled when no signal (info
0) is present on the S bus and the C/I command is ’1111’ = DIU (refer to chapter 3.6.2).
If the TE wants to activate the line, it has first to activate the IOM-2 interface either by
using the "Software Power Up" function (SPCR:SPU bit) or by setting the CFS bit to "0"
again.
For the TE case the deactivation procedure is shown in figure 90. After detecting the
code DIU (Deactivate Indication Upstream) the layer 1 of the IPAC responds by
transmitting DID (Deactivate Indication Downstream) during subsequent frames and
stops the timing signals synchronously with the end of the last C/I (C/I0) channel bit of
the fourth frame.
3.6
3.6.1
Semiconductor Group
Control of Layer-1
Activation/Deactivation of IOM
188
®
-2 Interface
Operational Description
PSB 2115
PSF 2115
11.97