PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 228

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Depending on the result of this comparison, the following bit combinations are possible:
10 … RAH1 has been recognized
00 … RAH2 has been recognized
01 … group address has been recognized
HA1, HA0 … High Byte Address Compare; significant only if 2-byte address mode
has been selected.
In operating modes which provide high byte address recognition, the IPAC compares the
high byte of a 2-bytes address with the contents of two individual programmable
registers (RAH1, RAH2) and the fixed values FE
Note: If RAH1, RAH2 contain the identical values, the combination 00 will be omitted.
C/R … Command/Response; significant only, if 2-byte address mode has been
selected.
Value of the C/R bit (bit of high address byte) in the received frame.
0 ... response received
1 ... command received
LA … Low Byte Address Compare; not significant in transparent and extended
transparent operating modes.
The low byte address of a 2-byte address field, or the single address byte of a 1-byte
address field is compared with two programmable registers (RAL1, RAL2)
0 … RAL2 has been recognized
1 … RAL1 has been recognized
According to the X.25 LAPB protocol, RAL1 is interpreted as COMMAND and RAL2
interpreted as RESPONSE.
Note: RSTAB corresponds to the last received HDLC frame; it is duplicated into RFIFOB
Semiconductor Group
for every frame (last byte of frame).
If several frames are contained in the RFIFO the corresponding status information
for each frame should be evaluated from the FIFO contents (last byte) as RSTAB
only refers to last frame in the FIFO.
228
H
and FC
Detailed Register Description
H
(group address).
PSB 2115
PSF 2115
11.97