PEB3086FV14XP Lantiq, PEB3086FV14XP Datasheet - Page 222

• Manufacturer Part Number: PEB3086FV14XP
• Manufacturer: Lantiq

Specifications of PEB3086FV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

EXMB
RAC ... Receiver Active
The B-channel HDLC receiver is activated when this bit is set to ’1’. If set to ’0’ the HDLC
data is not evaluated in the receiver.
4.6.6
Value after reset: C0
RFBS … Receive FIFO Block Size
0 … Block size is 16 byte
1 … Block size is 8 byte
Note: A change of RFBS will take effect after a transmitter command (CMDRB.RMC,
SRA … Store Receive Address
0 … Receive Address is not stored in the RFIFOB
1 … Receive Address is stored in the RFIFOB
XCRC … Transmit CRC
0 … CRC is transmitted
1 … CRC is not transmitted
RCRC… Receive CRC
0 … CRC is not stored in the RFIFOB
1 … CRC is stored in the RFIFOB
ITF… Interframe Time Fill
Selects the inter-frame time fill signal which is transmitted between HDLC-frames.
0 … idle (continuous ’1’)
1 … flags (sequence of patterns: ‘0111 1110’)
Data Sheet
CMDRB.RRES,) has been written
The transmit FIFO block size is fixed to 32 byte and cannot be configured.
7
EXMB - Extended Mode Register B-Channel
1
H
1
RFBS
SRA XCRC RCRC
222
Detailed Register Description
0
0
ITF
PEB 3086
2003-01-30
ISAC-SX
RD/WR
(73)