PEB3086FV14XP Lantiq, PEB3086FV14XP Datasheet - Page 14

• Manufacturer Part Number: PEB3086FV14XP
• Manufacturer: Lantiq

Specifications of PEB3086FV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Table 1
Operating modes
Supply voltage
Technology
Package
Transceiver
Transformer ratio for the
transmitter
receiver
Test Functions
Microcontroller Interface
Command structure of the
register access (SCI)
Crystal
Buffered 7.68 MHz output
Controller data access to
IOM-2 timeslots
Data control and
manipulation
IOM-2
Data Sheet
Comparison of the ISAC-SX with the Previous Version ISAC-S
ISAC-SX PEB 3086
TE, LT-T, LT-S, NT, Int. NT TE, LT-T, LT-S, NT
3.3 V ± 5%
CMOS
P-MQFP-64 / P-TQFP-64
1:1
1:1
- Dig. loop via Layer 2 (TLP)
- Layer 1 disable (DIS_TR)
- Analog loop (LP_A- bit
Serial interface (SCI)
8-bit parallel interface:
Motorola Mux
Siemens/Intel Mux
Siemens/Intel Non-Mux
direct/ indirect Addressing
Header/address/data
7.68 MHz
Provided
All timeslots;
various possibilities of data
access
Various possibilities of data
control and data
manipulation (enable/
disable, shifting, looping,
switching)
EXLP- bit, ARL)
14
ISAC-S PEB 2086
5 V ± 5%
CMOS
P-MQFP-64 / P-LCC-44
2:1
2:1
- Dig. loop via Layer 2(TLP)
- Layer 1 disable (DIS_TR)
- Analog loop (ARL)
Not provided
8-bit parallel interface:
Motorola Mux
Siemens/Intel Mux
Siemens/Intel Non-Mux
Address/data
7.68 MHz
Not provided
Restricted access to
B- and IC-channel
B- and IC-channel looping
PEB 3086
2003-01-30
ISAC-SX
Overview