PEB3086FV14XP Lantiq, PEB3086FV14XP Datasheet - Page 219

• Manufacturer Part Number: PEB3086FV14XP
• Manufacturer: Lantiq

Specifications of PEB3086FV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MASKB
STARB
XDU ... Transmit Data Underrun
The current transmission of a frame is aborted by transmitting seven ’1’s because the
XFIFOB holds no further data. This interrupt occurs whenever the microcontroller has
failed to respond to an XPR interrupt (ISTAB register) quickly enough, after having
initiated a transmission and the message to be transmitted is not yet complete.
4.6.2
Value after reset: FF
Each interrupt source in the ISTAB register can selectively be masked by setting the
corresponding bit in MASKB to ’1’. Masked interrupt status bits are not indicated when
ISTAB is read. Instead, they remain internally stored and pending until the mask bit is
reset to ’0’.
For general information please refer to
4.6.3
Value after reset: 40
XDOV ... Transmit Data Overflow
More than 32 bytes have been written to the XFIFOB, i.e. data has been overwritten.
XFW ... Transmit FIFO Write Enable
Data can be written to the XFIFOB. This bit may be polled instead of (or in addition to)
using the XPR interrupt.
RACI ... Receiver Active Indication
The B-channel HDLC receiver is active when RACI = ’1’. This bit may be polled. The
RACI bit is set active after a begin flag has been received and is reset after receiving an
abort sequence.
Data Sheet
7
7
XDOV XFW
MASKB - Mask Register B-Channel
STARB - Status Register B-Channel
RME
RPF
H
H
RFO
0
XPR
0
Chapter
219
RACI
1
3.8.7.
XDU
0
Detailed Register Description
XACI
1
0
0
1
0
PEB 3086
2003-01-30
ISAC-SX
WR (70)
RD (71)