PEB3086FV14XP Lantiq, PEB3086FV14XP Datasheet - Page 170

• Manufacturer Part Number: PEB3086FV14XP
• Manufacturer: Lantiq

Specifications of PEB3086FV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

EXMD1
RAC ... Receiver Active
The D-channel HDLC receiver is activated when this bit is set to ’1’. If set to ’0’ the HDLC
data is not evaluated in the receiver.
DIM2-0 ... Digital Interface Modes
These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit
enables/disables the collission detection. The DIM1 bit enables/disables the TIC bus
access. The effect of the individual DIM bits is summarized in the table below.
DIM2
0
0
0
0
1
4.1.8
Value after reset: 00
XFBS … Transmit FIFO Block Size
0 … Block size for the transmit FIFO data is 32 byte
1 … Block size for the transmit FIFO data is 16 byte
Note: A change of XFBS will take effect after a receiver command (CMDRD.XME,
Data Sheet
CMDRD.XRES, CMDRD.XTF) has been written.
DIM1 DIM0 Characteristics
0
1
x
7
EXMD1- Extended Mode Register D-Channel 1
XFBS
0
1
x
H
Transparent D-channel, the collission detection is disabled
Stop/go bit evaluated for D-channel access handling
Last octet of IOM channel 2 used for TIC bus access
TIC bus access is disabled
Reserved
RFBS
SRA XCRC RCRC
170
Detailed Register Description
0
0
ITF
RD/WR (23)
PEB 3086
2003-01-30
ISAC-SX