PEB3086FV14XP Lantiq, PEB3086FV14XP Datasheet - Page 122

• Manufacturer Part Number: PEB3086FV14XP
• Manufacturer: Lantiq

Specifications of PEB3086FV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 65
The arbitration mechanism is implemented in the last octet in IOM-2 channel 2 of the
IOM-2 interface (see
generated by software (µP access to the C/I channel) or by the ISAC-SX itself
(transmission of an HDLC frame in the D-channel). A software access request to the bus
is effected by setting the BAC bit (CIX0 register) to ’1’.
In the case of an access request, the ISAC-SX checks the Bus Accessed-bit BAC (bit 5
of last octet of CH2 on DU, see
by a logical ’1’. If the bus is free, the ISAC-SX transmits its individual TIC bus address
TAD programmed in the CIX0 register (CIX0.TBA2-0). The ISAC-SX sends its TIC bus
address TAD and compares it bit by bit with the value on DU. If a sent bit set to ’1’ is read
back as ’0’ because of the access of another D-channel source with a lower TAD, the
ISAC-SX withdraws immediately from the TIC bus, i.e. the remaining TAD bits are not
transmitted. The TIC bus is occupied by the device which sends its address error-free.
If more than one device attempt to seize the bus simultaneously, the one with the lowest
address values wins. This one will set BAC=0 on TIC bus and starts D-channel
transmission in the same frame.
Data Sheet
D-channel
control
ICC (7)
ICC (2)
ICC (1)
.
.
.
Applications of TIC Bus in IOM-2 Bus Configuration
Figure
TIC-Bus
on IOM-2
transceiver
66). An access request to the TIC bus may either be
Figure
S-
66) for the status "bus free“, which is indicated
122
S-Interface
Description of Functional Blocks
NT
3086_09
U-Interface
PEB 3086
2003-01-30
ISAC-SX