PEB3086FV14XP Lantiq, PEB3086FV14XP Datasheet - Page 152

• Manufacturer Part Number: PEB3086FV14XP
• Manufacturer: Lantiq

Specifications of PEB3086FV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

ISAC-SX
PEB 3086
Description of Functional Blocks
Transmitter
The transmitter sends the data out of the FIFO without manipulation. Transmission is
always IOM-2 frame aligned and byte aligned, i.e. transmission starts in the first selected
channel (B1, B2, D, according to the setting of register DCI_CR or BCH_CR in the IOM-2
Handler) of the next IOM-2 frame.
The FIFO indications and commands are the same as in other modes.
If the microcontroller sets XTF & XME the transmitter responds with an XPR interrupt
after sending the last byte, then it returns to its idle state (sending continuous ‘1’).
If the collision detection is enabled in D-channel (MODE.DIM = ’0x1’) the stop go bit (S/
G) can be used as clear to send indication as in any other mode. If the S/G bit is set to
’1’ (stop) during transmission the transmitter responds always with an XMR (transmit
message repeat) interrupt.
If the microcontroller fails to respond to a XPR interrupt in time and the transmitter runs
out of data then it will assert an XDU (transmit data underrun) interrupt.
Receiver
The reception is IOM-2 frame aligned and byte aligned, like transmission, i.e. reception
starts in the first selected channel (B1, B2, D, according to the setting of registers
DCI_CR and BCH_CR in the IOM-2 Handler) of the next IOM-2 frame. The FIFO
indications and commands are the same as in others modes.
All incoming data bytes are stored in the RFIFOx and is additionally made available in
RSTAx. If the FIFO is full an RFO interrupt is asserted (EXMx.SRA = ’0’).
Note: In the extended transparent mode the EXMx register has to be set to ’xxx00000’
Data Sheet
152
2003-01-30