WM8310GEB/V Wolfson Microelectronics, WM8310GEB/V Datasheet - Page 48

• Manufacturer Part Number: WM8310GEB/V
• Description: POWER MANAGEMENT SUBSYSTEM, 169BGA
• Manufacturer: Wolfson Microelectronics

Specifications of WM8310GEB/V

• Supply Voltage: 7V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 11
• Digital Ic Case Style: BGA
• No. Of Pins: 169
• No. Of Regulated Outputs: 13
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

WM8310
13.3 FREQUENCY LOCKED LOOP (FLL)
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The integrated FLL can be used to generate a clock on the CLKOUT pin from a wide variety of
different reference sources and frequencies. The FLL can use either CLKIN or the 32.768kHz
oscillator as its reference. A wide range of CLKIN frequencies can be supported; this may be a high
frequency (eg. 12.288MHz) or low frequency (eg. 32.768kHz) reference. The FLL is tolerant of jitter
and may be used to generate a stable clock reference from a less stable input signal. The FLL
characteristics are summarised in “Electrical Characteristics”.
To simplify the configuration of the FLL, an ‘automatic’ mode is provided in order to synthesize a
number of commonly used reference frequencies using the 32.768kHz crystal oscillator as a
reference.
The FLL is enabled using the FLL_ENA register bit. Note that, when changing FLL settings, it is
recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other
register settings have been updated. When changing the input reference frequency F
recommended that the FLL be reset by setting FLL_ENA to 0.
The FLL input reference is configured using the FLL_CLK_SRC register bit. The available sources
are the CLKIN pin or the 32.768kHz crystal oscillator.
The field FLL_CLK_REF_DIV provides the option to divide the selected input reference by 1, 2, 4 or
8. This field should be set to bring the reference down to 13.5MHz or below. For best performance, it
is recommended that the highest possible frequency - within the 13.5MHz limit - should be selected.
The field FLL_CTRL_RATE controls internal functions within the FLL; it is recommended that only
the default setting be used for this parameter. FLL_GAIN controls the internal loop gain and should
be set to the recommended value quoted in Table 20.
The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real
number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the
fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the
field FLL_FRAC.
Power consumption in the FLL is reduced in integer mode; however, the performance may also be
reduced, with increased noise or jitter on the output.
If low power consumption is required, then FLL settings must be chosen where N.K is an integer (ie.
FLL_K = 0). In this case, the fractional mode can be disabled by setting FLL_FRAC = 0.
For best FLL performance, a non-integer value of N.K is required. In this case, the fractional mode
must be enabled by setting FLL_FRAC = 1. The FLL settings must be adjusted, if necessary, to
produce a non-integer value of N.K.
The FLL output frequency is generated according to the following equation:
The FLL operating frequency, F
See Table 20 for the coding of the FLL_OUTDIV and FLL_FRATIO fields.
F
F
Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed
across the full range of device operating temperatures.
REF
VCO
is the input frequency, as determined by FLL_CLK_REF_DIV.
must be in the range 90-100 MHz. Frequencies outside this range cannot be supported.
F
F
OUT
VCO
= (F
= (F
VCO
REF
/ FLL_OUTDIV)
x N.K x FLL_FRATIO)
VCO
is set according to the following equation:
PP, December 2009, Rev 3.0
Pre-Production
REF
, it is
48