WM8310GEB/V Wolfson Microelectronics, WM8310GEB/V Datasheet - Page 140

• Manufacturer Part Number: WM8310GEB/V
• Description: POWER MANAGEMENT SUBSYSTEM, 169BGA
• Manufacturer: Wolfson Microelectronics

Specifications of WM8310GEB/V

• Supply Voltage: 7V
• No. Of Step-down Dc - Dc Converters: 4
• No. Of Ldo Regulators: 11
• Digital Ic Case Style: BGA
• No. Of Pins: 169
• No. Of Regulated Outputs: 13
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

WM8310
23 INTERRUPT CONTROLLER
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The WM8310 has a comprehensive Interrupt logic capability. The dedicated IRQ
alert a host processor to selected events or fault conditions. Each of the interrupt conditions can be
individually enabled or masked. Following an interrupt event, the host processor should read the
interrupt registers in order to determine what caused the interrupt, and take appropriate action if
required.
The WM8310 interrupt controller has two levels:
Secondary interrupts indicate a single event in one of the circuit blocks. The event is indicated by
setting a register bit. This bit is a latching bit - once it is set, it remains at logic 1 even if the trigger
condition is cleared. The secondary interrupts are cleared by writing a logic 1 to the relevant register
bit. Note that reading the register does not clear the secondary interrupt.
Primary interrupts are the logical OR of the associated secondary interrupts (usually all the interrupts
associated with one particular circuit block). Each of the secondary interrupts can be individually
masked or enabled as an input to the corresponding primary interrupt. The primary interrupt register
R16400 (4010h) is read-only.
The status of the IRQ
one or more of the primary interrupts is asserted. Each of the primary interrupts can be individually
masked or enabled as an input to the IRQ
The IRQ
IRQ_OD register bit. When the IRQ
circuit when not asserted. An external pull-up resistor may be required in the Open Drain mode.
The IRQ
it is held in the logic 1 (or Open Drain) state regardless of any internal interrupt event.
Note that the secondary interrupt bits are always valid - they are set as normal, regardless of whether
the bit is enabled or masked as an input to the corresponding primary interrupt. The primary interrupt
bits are set and cleared as normal in response to any unmasked secondary interrupt, regardless of
whether the primary interrupt bit is enabled or masked as an input to the IRQ
Note also that if any internal condition is configured to trigger an event other than an Interrupt (eg.
the Watchdog timer triggers Reset), these events are always actioned, regardless of the state of any
interrupt mask bits.
The IRQ
R16407
(4017h)
IRQ Config
Table 85 IRQ Pin Configuration
ADDRESS
¯ ¯ ¯ pin output can be masked by setting the IM_IRQ register bit. When the IRQ
¯ ¯ ¯ pin output is configured using the register bits desribed in Table 85.
¯ ¯ ¯ pin output can either be CMOS driven or Open Drain configuration, as determined by the
¯ ¯ ¯ pin reflects the logical NOR of the primary interrupts. A logic 0 indicates that
BIT
1
0
IRQ_OD
IM_IRQ
¯ ¯ ¯ pin is Open Drain, it is pulled low when asserted and is open
¯ ¯ ¯ pin output.
LABEL
IRQ pin configuration
0 = CMOS
1 = Open Drain
IRQ pin output mask
0 = Normal
1 = IRQ output is masked
PP, December 2009, Rev 3.0
¯ ¯ ¯ pin output.
DESCRIPTION
¯ ¯ ¯ pin can be used to
¯ ¯ ¯ pin is masked,
Pre-Production
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