WM8310GEB/V Wolfson Microelectronics, WM8310GEB/V Datasheet - Page 153

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WM8310GEB/V

Manufacturer Part Number
WM8310GEB/V
Description
POWER MANAGEMENT SUBSYSTEM, 169BGA
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8310GEB/V

Supply Voltage
7V
No. Of Step-down Dc - Dc Converters
4
No. Of Ldo Regulators
11
Digital Ic Case Style
BGA
No. Of Pins
169
No. Of Regulated Outputs
13
Operating Temperature Range
-40°C To
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Pre-Production
24.2 HARDWARE RESET
24.3 SOFTWARE RESET
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The WM8310 asserts the RESET
RESET
¯ ¯ ¯ ¯ ¯ ¯ is held low for the duration of the shutdown sequence and is held low in the OFF state. In the
cases where Automatic Recovery is supported, RESET
successful completion of the startup sequence. The duration of the RESET
startup sequence has completed is governed by the RST_DUR register field described in
Section 11.7.
A Hardware Reset is triggered when an external source pulls the RESET
condition, the WM8310 transitions to the OFF state. The contents of the Register map are cleared to
default values, except for the RTC and software scratch registers, which are maintained. The
WM8310 will then automatically schedule an ON state transition to resume normal operation.
If the external source continues to pull the RESET
the ON state transition following the Hardware Reset. In this case, the WM8310 will mask the
external reset for up to 32 seconds. If the RESET
time, then the ON state transition is completed and the Hardware Reset input is valid again from this
point. If the RESET
32 seconds timeout. Recovery from this forced OFF condition cannot occur until the external reset
condition is de-asserted, followed by a valid ON event. If an ON event occurs before the external
reset is de-asserted, then start-up will be attempted, but the transition will be unsuccessful, causing a
return to the OFF state.
It is possible to mask the RESET
bit as described in Section 11.7.
A Software Reset is triggered by writing to Register 0000h, as described in Section 12.5. In this
event, the WM8310 asserts the RESET
the ON state, then the WM8310 will automatically return to the ON state following the Reset.
The SWRST_DLY register field determines whether a time delay is applied between the Software
Reset command and the resultant shutdown and start-up sequences. When the SWRST_DLY bit is
set, the programmable time delay PWRSTATE_DLY is applied before commencing the shutdown
sequence.
The timing of the Software Reset is illustrated in Figure 30. See Section 11.3 for a definition of the
PWRSTATE_DLY register.
The SW_RESET_CFG register field determines if the Register Map is reset under a Software Reset
condition.
Note that the SW_RESET_CFG control register is locked by the WM8310 User Key. This register
can only be changed by writing the appropriate code to the Security register, as described in
Section 12.4.
R16387
(4003h)
Power State
R16390
(4006h)
Reset
Control
Table 101 Software Reset Configuration
ADDRESS
¯ ¯ ¯ ¯ ¯ ¯ pin is not released, then the WM8310 will force an OFF condition on expiry of the
BIT
10
9
SWRST_DLY
SW_RESET_C
FG
¯ ¯ ¯ ¯ ¯ ¯ pin input in the SLEEP state by setting the RST_SLP_MSK register
LABEL
¯ ¯ ¯ ¯ ¯ ¯ low as soon as the device begins the shutdown sequence.
¯ ¯ ¯ ¯ ¯ ¯ pin and transitions to the OFF state. If the Reset occurred in
¯ ¯ ¯ ¯ ¯ ¯ pin is released (ie. it returns to logic ‘1’) during this
DEFAULT
¯ ¯ ¯ ¯ ¯ ¯ pin low, then the WM8310 cannot fully complete
0
1
¯ ¯ ¯ ¯ ¯ ¯ is automatically cleared (high) after
Software Reset Delay
0 = No delay
1 = Software Reset is delayed by
PWRSTATE_DLY following the Software
Reset command
Software Reset Configuration.
Selects whether the register map is reset to
default values when Software Reset occurs.
0 = All registers except RTC and Software
Scratch registers are reset by Software
Reset
1 = Register Map is not affected by Software
Reset
Protected by user key
DESCRIPTION
PP, December 2009, Rev 3.0
¯ ¯ ¯ ¯ ¯ ¯ low period after the
¯ ¯ ¯ ¯ ¯ ¯ pin low. Under this
WM8310
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